9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 */
30
31 #ifndef _IXGBE_SW_H
32 #define _IXGBE_SW_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <sys/types.h>
39 #include <sys/conf.h>
40 #include <sys/debug.h>
41 #include <sys/stropts.h>
42 #include <sys/stream.h>
43 #include <sys/strsun.h>
44 #include <sys/strlog.h>
45 #include <sys/kmem.h>
46 #include <sys/stat.h>
47 #include <sys/kstat.h>
48 #include <sys/modctl.h>
192 #define IPHDR_ALIGN_ROOM 2
193
194 /*
195 * Bit flags for attach_progress
196 */
197 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
198 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
199 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
200 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
201 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
202 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
203 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
204 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
205 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
206 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
207 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
208 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
209 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
210 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
211 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
212
213 #define PROP_DEFAULT_MTU "default_mtu"
214 #define PROP_FLOW_CONTROL "flow_control"
215 #define PROP_TX_QUEUE_NUM "tx_queue_number"
216 #define PROP_TX_RING_SIZE "tx_ring_size"
217 #define PROP_RX_QUEUE_NUM "rx_queue_number"
218 #define PROP_RX_RING_SIZE "rx_ring_size"
219 #define PROP_RX_GROUP_NUM "rx_group_number"
220
221 #define PROP_INTR_FORCE "intr_force"
222 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
223 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
224 #define PROP_LSO_ENABLE "lso_enable"
225 #define PROP_LRO_ENABLE "lro_enable"
226 #define PROP_MR_ENABLE "mr_enable"
227 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
228 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
229 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
230 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
231 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
612 int rxr_cnt; /* count rx rings */
613 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
614 int txr_cnt; /* count tx rings */
615 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
616 int other_cnt; /* count other interrupt */
617 } ixgbe_intr_vector_t;
618
619 /*
620 * Software adapter state
621 */
622 typedef struct ixgbe {
623 int instance;
624 mac_handle_t mac_hdl;
625 dev_info_t *dip;
626 struct ixgbe_hw hw;
627 struct ixgbe_osdep osdep;
628
629 adapter_info_t *capab; /* adapter hardware capabilities */
630 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
631 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
632 uint32_t eims; /* interrupt mask setting */
633 uint32_t eimc; /* interrupt mask clear */
634 uint32_t eicr; /* interrupt cause reg */
635
636 uint32_t ixgbe_state;
637 link_state_t link_state;
638 uint32_t link_speed;
639 uint32_t link_duplex;
640
641 uint32_t reset_count;
642 uint32_t attach_progress;
643 uint32_t loopback_mode;
644 uint32_t default_mtu;
645 uint32_t max_frame_size;
646
647 uint32_t rcb_pending;
648
649 /*
650 * Each msi-x vector: map vector to interrupt cleanup
651 */
652 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
653
654 /*
655 * Receive Rings
656 */
657 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
658 uint32_t num_rx_rings; /* Number of rx rings in use */
659 uint32_t rx_ring_size; /* Rx descriptor ring size */
660 uint32_t rx_buf_size; /* Rx buffer size */
661 boolean_t lro_enable; /* Large Receive Offload */
662 uint64_t lro_pkt_count; /* LRO packet count */
663 /*
664 * Receive Groups
665 */
713
714 boolean_t unicst_init;
715 uint32_t unicst_avail;
716 uint32_t unicst_total;
717 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
718 uint32_t mcast_count;
719 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
720
721 ulong_t sys_page_size;
722
723 boolean_t link_check_complete;
724 hrtime_t link_check_hrtime;
725 ddi_periodic_t periodic_id; /* for link check timer func */
726
727 /*
728 * Kstat definitions
729 */
730 kstat_t *ixgbe_ks;
731
732 uint32_t param_en_10000fdx_cap:1,
733 param_en_1000fdx_cap:1,
734 param_en_100fdx_cap:1,
735 param_adv_10000fdx_cap:1,
736 param_adv_1000fdx_cap:1,
737 param_adv_100fdx_cap:1,
738 param_pause_cap:1,
739 param_asym_pause_cap:1,
740 param_rem_fault:1,
741 param_adv_autoneg_cap:1,
742 param_adv_pause_cap:1,
743 param_adv_asym_pause_cap:1,
744 param_adv_rem_fault:1,
745 param_lp_10000fdx_cap:1,
746 param_lp_1000fdx_cap:1,
747 param_lp_100fdx_cap:1,
748 param_lp_autoneg_cap:1,
749 param_lp_pause_cap:1,
750 param_lp_asym_pause_cap:1,
751 param_lp_rem_fault:1,
752 param_pad_to_32:12;
753 } ixgbe_t;
754
755 typedef struct ixgbe_stat {
756 kstat_named_t link_speed; /* Link Speed */
757
758 kstat_named_t reset_count; /* Reset Count */
759
760 kstat_named_t rx_frame_error; /* Rx Error in Packet */
761 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
762 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
763
764 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
765 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
766 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
767 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
768 kstat_named_t tx_reschedule; /* Tx Reschedule */
769
770 kstat_named_t gprc; /* Good Packets Received Count */
771 kstat_named_t gptc; /* Good Packets Xmitted Count */
772 kstat_named_t gor; /* Good Octets Received Count */
|
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 */
31
32 #ifndef _IXGBE_SW_H
33 #define _IXGBE_SW_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #include <sys/types.h>
40 #include <sys/conf.h>
41 #include <sys/debug.h>
42 #include <sys/stropts.h>
43 #include <sys/stream.h>
44 #include <sys/strsun.h>
45 #include <sys/strlog.h>
46 #include <sys/kmem.h>
47 #include <sys/stat.h>
48 #include <sys/kstat.h>
49 #include <sys/modctl.h>
193 #define IPHDR_ALIGN_ROOM 2
194
195 /*
196 * Bit flags for attach_progress
197 */
198 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
199 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
200 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
201 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
202 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
203 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
204 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
205 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
206 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
207 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
208 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
209 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
210 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
211 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
212 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
213 #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
214
215 #define PROP_DEFAULT_MTU "default_mtu"
216 #define PROP_FLOW_CONTROL "flow_control"
217 #define PROP_TX_QUEUE_NUM "tx_queue_number"
218 #define PROP_TX_RING_SIZE "tx_ring_size"
219 #define PROP_RX_QUEUE_NUM "rx_queue_number"
220 #define PROP_RX_RING_SIZE "rx_ring_size"
221 #define PROP_RX_GROUP_NUM "rx_group_number"
222
223 #define PROP_INTR_FORCE "intr_force"
224 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
225 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
226 #define PROP_LSO_ENABLE "lso_enable"
227 #define PROP_LRO_ENABLE "lro_enable"
228 #define PROP_MR_ENABLE "mr_enable"
229 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
230 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
231 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
232 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
233 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
614 int rxr_cnt; /* count rx rings */
615 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
616 int txr_cnt; /* count tx rings */
617 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
618 int other_cnt; /* count other interrupt */
619 } ixgbe_intr_vector_t;
620
621 /*
622 * Software adapter state
623 */
624 typedef struct ixgbe {
625 int instance;
626 mac_handle_t mac_hdl;
627 dev_info_t *dip;
628 struct ixgbe_hw hw;
629 struct ixgbe_osdep osdep;
630
631 adapter_info_t *capab; /* adapter hardware capabilities */
632 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
633 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
634 ddi_taskq_t *phy_taskq; /* external PHY taskq */
635 uint32_t eims; /* interrupt mask setting */
636 uint32_t eimc; /* interrupt mask clear */
637 uint32_t eicr; /* interrupt cause reg */
638
639 uint32_t ixgbe_state;
640 link_state_t link_state;
641 uint32_t link_speed;
642 uint32_t link_duplex;
643
644 uint32_t reset_count;
645 uint32_t attach_progress;
646 uint32_t loopback_mode;
647 uint32_t default_mtu;
648 uint32_t max_frame_size;
649 ixgbe_link_speed speeds_supported;
650
651 uint32_t rcb_pending;
652
653 /*
654 * Each msi-x vector: map vector to interrupt cleanup
655 */
656 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
657
658 /*
659 * Receive Rings
660 */
661 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
662 uint32_t num_rx_rings; /* Number of rx rings in use */
663 uint32_t rx_ring_size; /* Rx descriptor ring size */
664 uint32_t rx_buf_size; /* Rx buffer size */
665 boolean_t lro_enable; /* Large Receive Offload */
666 uint64_t lro_pkt_count; /* LRO packet count */
667 /*
668 * Receive Groups
669 */
717
718 boolean_t unicst_init;
719 uint32_t unicst_avail;
720 uint32_t unicst_total;
721 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
722 uint32_t mcast_count;
723 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
724
725 ulong_t sys_page_size;
726
727 boolean_t link_check_complete;
728 hrtime_t link_check_hrtime;
729 ddi_periodic_t periodic_id; /* for link check timer func */
730
731 /*
732 * Kstat definitions
733 */
734 kstat_t *ixgbe_ks;
735
736 uint32_t param_en_10000fdx_cap:1,
737 param_en_5000fdx_cap:1,
738 param_en_2500fdx_cap:1,
739 param_en_1000fdx_cap:1,
740 param_en_100fdx_cap:1,
741 param_adv_10000fdx_cap:1,
742 param_adv_5000fdx_cap:1,
743 param_adv_2500fdx_cap:1,
744 param_adv_1000fdx_cap:1,
745 param_adv_100fdx_cap:1,
746 param_pause_cap:1,
747 param_asym_pause_cap:1,
748 param_rem_fault:1,
749 param_adv_autoneg_cap:1,
750 param_adv_pause_cap:1,
751 param_adv_asym_pause_cap:1,
752 param_adv_rem_fault:1,
753 param_lp_10000fdx_cap:1,
754 param_lp_5000fdx_cap:1,
755 param_lp_2500fdx_cap:1,
756 param_lp_1000fdx_cap:1,
757 param_lp_100fdx_cap:1,
758 param_lp_autoneg_cap:1,
759 param_lp_pause_cap:1,
760 param_lp_asym_pause_cap:1,
761 param_lp_rem_fault:1,
762 param_pad_to_32:6;
763 } ixgbe_t;
764
765 typedef struct ixgbe_stat {
766 kstat_named_t link_speed; /* Link Speed */
767
768 kstat_named_t reset_count; /* Reset Count */
769
770 kstat_named_t rx_frame_error; /* Rx Error in Packet */
771 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
772 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
773
774 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
775 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
776 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
777 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
778 kstat_named_t tx_reschedule; /* Tx Reschedule */
779
780 kstat_named_t gprc; /* Good Packets Received Count */
781 kstat_named_t gptc; /* Good Packets Xmitted Count */
782 kstat_named_t gor; /* Good Octets Received Count */
|