1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 */
31
32 #ifndef _IXGBE_SW_H
33 #define _IXGBE_SW_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #include <sys/types.h>
40 #include <sys/conf.h>
41 #include <sys/debug.h>
42 #include <sys/stropts.h>
43 #include <sys/stream.h>
44 #include <sys/strsun.h>
45 #include <sys/strlog.h>
46 #include <sys/kmem.h>
47 #include <sys/stat.h>
48 #include <sys/kstat.h>
49 #include <sys/modctl.h>
50 #include <sys/errno.h>
51 #include <sys/dlpi.h>
52 #include <sys/mac_provider.h>
53 #include <sys/mac_ether.h>
54 #include <sys/vlan.h>
55 #include <sys/ddi.h>
56 #include <sys/sunddi.h>
57 #include <sys/pci.h>
58 #include <sys/pcie.h>
59 #include <sys/sdt.h>
60 #include <sys/ethernet.h>
61 #include <sys/pattr.h>
62 #include <sys/strsubr.h>
63 #include <sys/netlb.h>
64 #include <sys/random.h>
65 #include <inet/common.h>
66 #include <inet/tcp.h>
67 #include <inet/ip.h>
68 #include <inet/mi.h>
69 #include <inet/nd.h>
70 #include <sys/bitmap.h>
71 #include <sys/ddifm.h>
72 #include <sys/fm/protocol.h>
73 #include <sys/fm/util.h>
74 #include <sys/disp.h>
75 #include <sys/fm/io/ddi.h>
76 #include "ixgbe_api.h"
77
78 #define MODULE_NAME "ixgbe" /* module name */
79
80 #define IXGBE_FAILURE DDI_FAILURE
81
82 #define IXGBE_UNKNOWN 0x00
83 #define IXGBE_INITIALIZED 0x01
84 #define IXGBE_STARTED 0x02
85 #define IXGBE_SUSPENDED 0x04
86 #define IXGBE_STALL 0x08
87 #define IXGBE_OVERTEMP 0x20
88 #define IXGBE_INTR_ADJUST 0x40
89 #define IXGBE_ERROR 0x80
90
91 #define MAX_NUM_UNICAST_ADDRESSES 0x80
92 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
93 #define IXGBE_INTR_NONE 0
94 #define IXGBE_INTR_MSIX 1
95 #define IXGBE_INTR_MSI 2
96 #define IXGBE_INTR_LEGACY 3
97
98 #define IXGBE_POLL_NULL -1
99
100 #define MAX_COOKIE 18
101 #define MIN_NUM_TX_DESC 2
102
103 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
104
105 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
106
107 #define IXGBE_RX_STOPPED 0x1
108
109 #define IXGBE_PKG_BUF_16k 16384
110
111 /*
112 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
113 * supported silicon types.
114 */
115 #define MAX_TX_QUEUE_NUM 128
116 #define MAX_RX_QUEUE_NUM 128
117 #define MAX_INTR_VECTOR 64
118
119 /*
120 * Maximum values for user configurable parameters
121 */
122 #define MAX_TX_RING_SIZE 4096
123 #define MAX_RX_RING_SIZE 4096
124
125 #define MAX_RX_LIMIT_PER_INTR 4096
126
127 #define MAX_RX_COPY_THRESHOLD 9216
128 #define MAX_TX_COPY_THRESHOLD 9216
129 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
130 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
131 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
132
133 /*
134 * Minimum values for user configurable parameters
135 */
136 #define MIN_TX_RING_SIZE 64
137 #define MIN_RX_RING_SIZE 64
138
139 #define MIN_MTU ETHERMIN
140 #define MIN_RX_LIMIT_PER_INTR 16
141 #define MIN_TX_COPY_THRESHOLD 0
142 #define MIN_RX_COPY_THRESHOLD 0
143 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
144 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
145 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
146
147 /*
148 * Default values for user configurable parameters
149 */
150 #define DEFAULT_TX_RING_SIZE 1024
151 #define DEFAULT_RX_RING_SIZE 1024
152
153 #define DEFAULT_MTU ETHERMTU
154 #define DEFAULT_RX_LIMIT_PER_INTR 256
155 #define DEFAULT_RX_COPY_THRESHOLD 128
156 #define DEFAULT_TX_COPY_THRESHOLD 512
157 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
158 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
159 #define DEFAULT_TX_RESCHED_THRESHOLD 128
160 #define DEFAULT_FCRTH 0x20000
161 #define DEFAULT_FCRTL 0x10000
162 #define DEFAULT_FCPAUSE 0xFFFF
163
164 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
165 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
166 #define DEFAULT_LSO_ENABLE B_TRUE
167 #define DEFAULT_LRO_ENABLE B_FALSE
168 #define DEFAULT_MR_ENABLE B_TRUE
169 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
170 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
171 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
172
173 #define IXGBE_LSO_MAXLEN 65535
174
175 #define TX_DRAIN_TIME 200
176 #define RX_DRAIN_TIME 200
177
178 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
179 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
180
181 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
182
183 /*
184 * Extra register bit masks for 82598
185 */
186 #define IXGBE_PCS1GANA_FDC 0x20
187 #define IXGBE_PCS1GANLP_LPFD 0x20
188 #define IXGBE_PCS1GANLP_LPHD 0x40
189
190 /*
191 * Defined for IP header alignment.
192 */
193 #define IPHDR_ALIGN_ROOM 2
194
195 /*
196 * Bit flags for attach_progress
197 */
198 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
199 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
200 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
201 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
202 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
203 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
204 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
205 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
206 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
207 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
208 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
209 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
210 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
211 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
212 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
213 #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
214
215 #define PROP_DEFAULT_MTU "default_mtu"
216 #define PROP_FLOW_CONTROL "flow_control"
217 #define PROP_TX_QUEUE_NUM "tx_queue_number"
218 #define PROP_TX_RING_SIZE "tx_ring_size"
219 #define PROP_RX_QUEUE_NUM "rx_queue_number"
220 #define PROP_RX_RING_SIZE "rx_ring_size"
221 #define PROP_RX_GROUP_NUM "rx_group_number"
222
223 #define PROP_INTR_FORCE "intr_force"
224 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
225 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
226 #define PROP_LSO_ENABLE "lso_enable"
227 #define PROP_LRO_ENABLE "lro_enable"
228 #define PROP_MR_ENABLE "mr_enable"
229 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
230 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
231 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
232 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
233 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
234 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
235 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
236 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
237 #define PROP_INTR_THROTTLING "intr_throttling"
238 #define PROP_FM_CAPABLE "fm_capable"
239 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
240
241 #define IXGBE_LB_NONE 0
242 #define IXGBE_LB_EXTERNAL 1
243 #define IXGBE_LB_INTERNAL_MAC 2
244 #define IXGBE_LB_INTERNAL_PHY 3
245 #define IXGBE_LB_INTERNAL_SERDES 4
246
247 /*
248 * capability/feature flags
249 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
250 * Separately, the flag named _ENABLED is set when the feature is enabled.
251 */
252 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
253 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
254 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
255 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
256 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
257 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
258 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
259 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
260 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
261 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
262 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
263 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
264
265 /*
266 * Classification mode
267 */
268 #define IXGBE_CLASSIFY_NONE 0
269 #define IXGBE_CLASSIFY_RSS 1
270 #define IXGBE_CLASSIFY_VMDQ 2
271 #define IXGBE_CLASSIFY_VMDQ_RSS 3
272
273 /* adapter-specific info for each supported device type */
274 typedef struct adapter_info {
275 uint32_t max_rx_que_num; /* maximum number of rx queues */
276 uint32_t min_rx_que_num; /* minimum number of rx queues */
277 uint32_t def_rx_que_num; /* default number of rx queues */
278 uint32_t max_rx_grp_num; /* maximum number of rx groups */
279 uint32_t min_rx_grp_num; /* minimum number of rx groups */
280 uint32_t def_rx_grp_num; /* default number of rx groups */
281 uint32_t max_tx_que_num; /* maximum number of tx queues */
282 uint32_t min_tx_que_num; /* minimum number of tx queues */
283 uint32_t def_tx_que_num; /* default number of tx queues */
284 uint32_t max_mtu; /* maximum MTU size */
285 /*
286 * Interrupt throttling is in unit of 256 nsec
287 */
288 uint32_t max_intr_throttle; /* maximum interrupt throttle */
289 uint32_t min_intr_throttle; /* minimum interrupt throttle */
290 uint32_t def_intr_throttle; /* default interrupt throttle */
291
292 uint32_t max_msix_vect; /* maximum total msix vectors */
293 uint32_t max_ring_vect; /* maximum number of ring vectors */
294 uint32_t max_other_vect; /* maximum number of other vectors */
295 uint32_t other_intr; /* "other" interrupt types handled */
296 uint32_t other_gpie; /* "other" interrupt types enabling */
297 uint32_t flags; /* capability flags */
298 } adapter_info_t;
299
300 /* bits representing all interrupt types other than tx & rx */
301 #define IXGBE_OTHER_INTR 0x3ff00000
302 #define IXGBE_82599_OTHER_INTR 0x86100000
303
304 enum ioc_reply {
305 IOC_INVAL = -1, /* bad, NAK with EINVAL */
306 IOC_DONE, /* OK, reply sent */
307 IOC_ACK, /* OK, just send ACK */
308 IOC_REPLY /* OK, just send reply */
309 };
310
311 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
312 0, 0, (flag)))
313
314 /*
315 * Defined for ring index operations
316 * ASSERT(index < limit)
317 * ASSERT(step < limit)
318 * ASSERT(index1 < limit)
319 * ASSERT(index2 < limit)
320 */
321 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
322 (index) + (step) : (index) + (step) - (limit))
323 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
324 (index) - (step) : (index) + (limit) - (step))
325 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
326 (index2) - (index1) : (index2) + (limit) - (index1))
327
328 #define LINK_LIST_INIT(_LH) \
329 (_LH)->head = (_LH)->tail = NULL
330
331 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
332
333 #define LIST_POP_HEAD(_LH) \
334 (single_link_t *)(_LH)->head; \
335 { \
336 if ((_LH)->head != NULL) { \
337 (_LH)->head = (_LH)->head->link; \
338 if ((_LH)->head == NULL) \
339 (_LH)->tail = NULL; \
340 } \
341 }
342
343 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
344
345 #define LIST_PUSH_TAIL(_LH, _E) \
346 if ((_LH)->tail != NULL) { \
347 (_LH)->tail->link = (single_link_t *)(_E); \
348 (_LH)->tail = (single_link_t *)(_E); \
349 } else { \
350 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
351 } \
352 (_E)->link = NULL;
353
354 #define LIST_GET_NEXT(_LH, _E) \
355 (((_LH)->tail == (single_link_t *)(_E)) ? \
356 NULL : ((single_link_t *)(_E))->link)
357
358
359 typedef struct single_link {
360 struct single_link *link;
361 } single_link_t;
362
363 typedef struct link_list {
364 single_link_t *head;
365 single_link_t *tail;
366 } link_list_t;
367
368 /*
369 * Property lookups
370 */
371 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
372 DDI_PROP_DONTPASS, (n))
373 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
374 DDI_PROP_DONTPASS, (n), -1)
375
376
377 typedef union ixgbe_ether_addr {
378 struct {
379 uint32_t high;
380 uint32_t low;
381 } reg;
382 struct {
383 uint8_t set;
384 uint8_t group_index;
385 uint8_t addr[ETHERADDRL];
386 } mac;
387 } ixgbe_ether_addr_t;
388
389 typedef enum {
390 USE_NONE,
391 USE_COPY,
392 USE_DMA
393 } tx_type_t;
394
395 typedef struct ixgbe_tx_context {
396 uint32_t hcksum_flags;
397 uint32_t ip_hdr_len;
398 uint32_t mac_hdr_len;
399 uint32_t l4_proto;
400 uint32_t mss;
401 uint32_t l4_hdr_len;
402 boolean_t lso_flag;
403 } ixgbe_tx_context_t;
404
405 /*
406 * Hold address/length of each DMA segment
407 */
408 typedef struct sw_desc {
409 uint64_t address;
410 size_t length;
411 } sw_desc_t;
412
413 /*
414 * Handles and addresses of DMA buffer
415 */
416 typedef struct dma_buffer {
417 caddr_t address; /* Virtual address */
418 uint64_t dma_address; /* DMA (Hardware) address */
419 ddi_acc_handle_t acc_handle; /* Data access handle */
420 ddi_dma_handle_t dma_handle; /* DMA handle */
421 size_t size; /* Buffer size */
422 size_t len; /* Data length in the buffer */
423 } dma_buffer_t;
424
425 /*
426 * Tx Control Block
427 */
428 typedef struct tx_control_block {
429 single_link_t link;
430 uint32_t last_index; /* last descriptor of the pkt */
431 uint32_t frag_num;
432 uint32_t desc_num;
433 mblk_t *mp;
434 tx_type_t tx_type;
435 ddi_dma_handle_t tx_dma_handle;
436 dma_buffer_t tx_buf;
437 sw_desc_t desc[MAX_COOKIE];
438 } tx_control_block_t;
439
440 /*
441 * RX Control Block
442 */
443 typedef struct rx_control_block {
444 mblk_t *mp;
445 uint32_t ref_cnt;
446 dma_buffer_t rx_buf;
447 frtn_t free_rtn;
448 struct ixgbe_rx_data *rx_data;
449 int lro_next; /* Index of next rcb */
450 int lro_prev; /* Index of previous rcb */
451 boolean_t lro_pkt; /* Flag for LRO rcb */
452 } rx_control_block_t;
453
454 /*
455 * Software Data Structure for Tx Ring
456 */
457 typedef struct ixgbe_tx_ring {
458 uint32_t index; /* Ring index */
459 uint32_t intr_vector; /* Interrupt vector index */
460 uint32_t vect_bit; /* vector's bit in register */
461
462 /*
463 * Mutexes
464 */
465 kmutex_t tx_lock;
466 kmutex_t recycle_lock;
467 kmutex_t tcb_head_lock;
468 kmutex_t tcb_tail_lock;
469
470 /*
471 * Tx descriptor ring definitions
472 */
473 dma_buffer_t tbd_area;
474 union ixgbe_adv_tx_desc *tbd_ring;
475 uint32_t tbd_head; /* Index of next tbd to recycle */
476 uint32_t tbd_tail; /* Index of next tbd to transmit */
477 uint32_t tbd_free; /* Number of free tbd */
478
479 /*
480 * Tx control block list definitions
481 */
482 tx_control_block_t *tcb_area;
483 tx_control_block_t **work_list;
484 tx_control_block_t **free_list;
485 uint32_t tcb_head; /* Head index of free list */
486 uint32_t tcb_tail; /* Tail index of free list */
487 uint32_t tcb_free; /* Number of free tcb in free list */
488
489 uint32_t *tbd_head_wb; /* Head write-back */
490 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *);
491
492 /*
493 * s/w context structure for TCP/UDP checksum offload
494 * and LSO.
495 */
496 ixgbe_tx_context_t tx_context;
497
498 /*
499 * Tx ring settings and status
500 */
501 uint32_t ring_size; /* Tx descriptor ring size */
502 uint32_t free_list_size; /* Tx free list size */
503
504 boolean_t reschedule;
505 uint32_t recycle_fail;
506 uint32_t stall_watchdog;
507
508 #ifdef IXGBE_DEBUG
509 /*
510 * Debug statistics
511 */
512 uint32_t stat_overload;
513 uint32_t stat_fail_no_tbd;
514 uint32_t stat_fail_no_tcb;
515 uint32_t stat_fail_dma_bind;
516 uint32_t stat_reschedule;
517 uint32_t stat_break_tbd_limit;
518 uint32_t stat_lso_header_fail;
519 #endif
520 uint64_t stat_obytes;
521 uint64_t stat_opackets;
522
523 mac_ring_handle_t ring_handle;
524
525 /*
526 * Pointer to the ixgbe struct
527 */
528 struct ixgbe *ixgbe;
529 } ixgbe_tx_ring_t;
530
531 /*
532 * Software Receive Ring
533 */
534 typedef struct ixgbe_rx_data {
535 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
536
537 /*
538 * Rx descriptor ring definitions
539 */
540 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
541 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */
542 uint32_t rbd_next; /* Index of next rx desc */
543
544 /*
545 * Rx control block list definitions
546 */
547 rx_control_block_t *rcb_area;
548 rx_control_block_t **work_list; /* Work list of rcbs */
549 rx_control_block_t **free_list; /* Free list of rcbs */
550 uint32_t rcb_head; /* Index of next free rcb */
551 uint32_t rcb_tail; /* Index to put recycled rcb */
552 uint32_t rcb_free; /* Number of free rcbs */
553
554 /*
555 * Rx sw ring settings and status
556 */
557 uint32_t ring_size; /* Rx descriptor ring size */
558 uint32_t free_list_size; /* Rx free list size */
559
560 uint32_t rcb_pending;
561 uint32_t flag;
562
563 uint32_t lro_num; /* Number of rcbs of one LRO */
564 uint32_t lro_first; /* Index of first LRO rcb */
565
566 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */
567 } ixgbe_rx_data_t;
568
569 /*
570 * Software Data Structure for Rx Ring
571 */
572 typedef struct ixgbe_rx_ring {
573 uint32_t index; /* Ring index */
574 uint32_t group_index; /* Group index */
575 uint32_t hw_index; /* h/w ring index */
576 uint32_t intr_vector; /* Interrupt vector index */
577 uint32_t vect_bit; /* vector's bit in register */
578
579 ixgbe_rx_data_t *rx_data; /* Rx software ring */
580
581 kmutex_t rx_lock; /* Rx access lock */
582
583 #ifdef IXGBE_DEBUG
584 /*
585 * Debug statistics
586 */
587 uint32_t stat_frame_error;
588 uint32_t stat_cksum_error;
589 uint32_t stat_exceed_pkt;
590 #endif
591 uint64_t stat_rbytes;
592 uint64_t stat_ipackets;
593
594 mac_ring_handle_t ring_handle;
595 uint64_t ring_gen_num;
596
597 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
598 } ixgbe_rx_ring_t;
599 /*
600 * Software Receive Ring Group
601 */
602 typedef struct ixgbe_rx_group {
603 uint32_t index; /* Group index */
604 mac_group_handle_t group_handle; /* call back group handle */
605 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
606 } ixgbe_rx_group_t;
607
608 /*
609 * structure to map interrupt cleanup to msi-x vector
610 */
611 typedef struct ixgbe_intr_vector {
612 struct ixgbe *ixgbe; /* point to my adapter */
613 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
614 int rxr_cnt; /* count rx rings */
615 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
616 int txr_cnt; /* count tx rings */
617 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
618 int other_cnt; /* count other interrupt */
619 } ixgbe_intr_vector_t;
620
621 /*
622 * Software adapter state
623 */
624 typedef struct ixgbe {
625 int instance;
626 mac_handle_t mac_hdl;
627 dev_info_t *dip;
628 struct ixgbe_hw hw;
629 struct ixgbe_osdep osdep;
630
631 adapter_info_t *capab; /* adapter hardware capabilities */
632 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
633 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
634 ddi_taskq_t *phy_taskq; /* external PHY taskq */
635 uint32_t eims; /* interrupt mask setting */
636 uint32_t eimc; /* interrupt mask clear */
637 uint32_t eicr; /* interrupt cause reg */
638
639 uint32_t ixgbe_state;
640 link_state_t link_state;
641 uint32_t link_speed;
642 uint32_t link_duplex;
643
644 uint32_t reset_count;
645 uint32_t attach_progress;
646 uint32_t loopback_mode;
647 uint32_t default_mtu;
648 uint32_t max_frame_size;
649 ixgbe_link_speed speeds_supported;
650
651 uint32_t rcb_pending;
652
653 /*
654 * Each msi-x vector: map vector to interrupt cleanup
655 */
656 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
657
658 /*
659 * Receive Rings
660 */
661 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
662 uint32_t num_rx_rings; /* Number of rx rings in use */
663 uint32_t rx_ring_size; /* Rx descriptor ring size */
664 uint32_t rx_buf_size; /* Rx buffer size */
665 boolean_t lro_enable; /* Large Receive Offload */
666 uint64_t lro_pkt_count; /* LRO packet count */
667 /*
668 * Receive Groups
669 */
670 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
671 uint32_t num_rx_groups; /* Number of rx groups in use */
672
673 /*
674 * Transmit Rings
675 */
676 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
677 uint32_t num_tx_rings; /* Number of tx rings in use */
678 uint32_t tx_ring_size; /* Tx descriptor ring size */
679 uint32_t tx_buf_size; /* Tx buffer size */
680
681 boolean_t tx_ring_init;
682 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
683 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
684 boolean_t lso_enable; /* Large Segment Offload */
685 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
686 boolean_t relax_order_enable; /* Relax Order */
687 uint32_t classify_mode; /* Classification mode */
688 uint32_t tx_copy_thresh; /* Tx copy threshold */
689 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
690 uint32_t tx_overload_thresh; /* Tx overload threshold */
691 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
692 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
693 uint32_t rx_copy_thresh; /* Rx copy threshold */
694 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
695 uint32_t intr_throttling[MAX_INTR_VECTOR];
696 uint32_t intr_force;
697 int fm_capabilities; /* FMA capabilities */
698
699 int intr_type;
700 int intr_cnt;
701 uint32_t intr_cnt_max;
702 uint32_t intr_cnt_min;
703 int intr_cap;
704 size_t intr_size;
705 uint_t intr_pri;
706 ddi_intr_handle_t *htable;
707 uint32_t eims_mask;
708 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
709
710 kmutex_t gen_lock; /* General lock for device access */
711 kmutex_t watchdog_lock;
712 kmutex_t rx_pending_lock;
713
714 boolean_t watchdog_enable;
715 boolean_t watchdog_start;
716 timeout_id_t watchdog_tid;
717
718 boolean_t unicst_init;
719 uint32_t unicst_avail;
720 uint32_t unicst_total;
721 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
722 uint32_t mcast_count;
723 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
724
725 ulong_t sys_page_size;
726
727 boolean_t link_check_complete;
728 hrtime_t link_check_hrtime;
729 ddi_periodic_t periodic_id; /* for link check timer func */
730
731 /*
732 * Kstat definitions
733 */
734 kstat_t *ixgbe_ks;
735
736 uint32_t param_en_10000fdx_cap:1,
737 param_en_5000fdx_cap:1,
738 param_en_2500fdx_cap:1,
739 param_en_1000fdx_cap:1,
740 param_en_100fdx_cap:1,
741 param_adv_10000fdx_cap:1,
742 param_adv_5000fdx_cap:1,
743 param_adv_2500fdx_cap:1,
744 param_adv_1000fdx_cap:1,
745 param_adv_100fdx_cap:1,
746 param_pause_cap:1,
747 param_asym_pause_cap:1,
748 param_rem_fault:1,
749 param_adv_autoneg_cap:1,
750 param_adv_pause_cap:1,
751 param_adv_asym_pause_cap:1,
752 param_adv_rem_fault:1,
753 param_lp_10000fdx_cap:1,
754 param_lp_5000fdx_cap:1,
755 param_lp_2500fdx_cap:1,
756 param_lp_1000fdx_cap:1,
757 param_lp_100fdx_cap:1,
758 param_lp_autoneg_cap:1,
759 param_lp_pause_cap:1,
760 param_lp_asym_pause_cap:1,
761 param_lp_rem_fault:1,
762 param_pad_to_32:6;
763 } ixgbe_t;
764
765 typedef struct ixgbe_stat {
766 kstat_named_t link_speed; /* Link Speed */
767
768 kstat_named_t reset_count; /* Reset Count */
769
770 kstat_named_t rx_frame_error; /* Rx Error in Packet */
771 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
772 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
773
774 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
775 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
776 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
777 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
778 kstat_named_t tx_reschedule; /* Tx Reschedule */
779
780 kstat_named_t gprc; /* Good Packets Received Count */
781 kstat_named_t gptc; /* Good Packets Xmitted Count */
782 kstat_named_t gor; /* Good Octets Received Count */
783 kstat_named_t got; /* Good Octets Xmitd Count */
784 kstat_named_t prc64; /* Packets Received - 64b */
785 kstat_named_t prc127; /* Packets Received - 65-127b */
786 kstat_named_t prc255; /* Packets Received - 127-255b */
787 kstat_named_t prc511; /* Packets Received - 256-511b */
788 kstat_named_t prc1023; /* Packets Received - 511-1023b */
789 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
790 kstat_named_t ptc64; /* Packets Xmitted (64b) */
791 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
792 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
793 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
794 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
795 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
796 kstat_named_t qprc[16]; /* Queue Packets Received Count */
797 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */
798 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */
799 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */
800
801 kstat_named_t crcerrs; /* CRC Error Count */
802 kstat_named_t illerrc; /* Illegal Byte Error Count */
803 kstat_named_t errbc; /* Error Byte Count */
804 kstat_named_t mspdc; /* MAC Short Packet Discard Count */
805 kstat_named_t mpc; /* Missed Packets Count */
806 kstat_named_t mlfc; /* MAC Local Fault Count */
807 kstat_named_t mrfc; /* MAC Remote Fault Count */
808 kstat_named_t rlec; /* Receive Length Error Count */
809 kstat_named_t lxontxc; /* Link XON Transmitted Count */
810 kstat_named_t lxonrxc; /* Link XON Received Count */
811 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
812 kstat_named_t lxoffrxc; /* Link XOFF Received Count */
813 kstat_named_t bprc; /* Broadcasts Pkts Received Count */
814 kstat_named_t mprc; /* Multicast Pkts Received Count */
815 kstat_named_t rnbc; /* Receive No Buffers Count */
816 kstat_named_t ruc; /* Receive Undersize Count */
817 kstat_named_t rfc; /* Receive Frag Count */
818 kstat_named_t roc; /* Receive Oversize Count */
819 kstat_named_t rjc; /* Receive Jabber Count */
820 kstat_named_t tor; /* Total Octets Recvd Count */
821 kstat_named_t tot; /* Total Octets Xmitted Count */
822 kstat_named_t tpr; /* Total Packets Received */
823 kstat_named_t tpt; /* Total Packets Xmitted */
824 kstat_named_t mptc; /* Multicast Packets Xmited Count */
825 kstat_named_t bptc; /* Broadcast Packets Xmited Count */
826 kstat_named_t lroc; /* LRO Packets Received Count */
827 } ixgbe_stat_t;
828
829 /*
830 * Function prototypes in ixgbe_buf.c
831 */
832 int ixgbe_alloc_dma(ixgbe_t *);
833 void ixgbe_free_dma(ixgbe_t *);
834 void ixgbe_set_fma_flags(int);
835 void ixgbe_free_dma_buffer(dma_buffer_t *);
836 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
837 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
838
839 /*
840 * Function prototypes in ixgbe_main.c
841 */
842 int ixgbe_start(ixgbe_t *, boolean_t);
843 void ixgbe_stop(ixgbe_t *, boolean_t);
844 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
845 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
846 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
847 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
848
849 void ixgbe_enable_watchdog_timer(ixgbe_t *);
850 void ixgbe_disable_watchdog_timer(ixgbe_t *);
851 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
852
853 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
854 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
855 void ixgbe_fm_ereport(ixgbe_t *, char *);
856
857 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
858 mac_ring_info_t *, mac_ring_handle_t);
859 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
860 mac_group_info_t *, mac_group_handle_t);
861 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
862 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
863
864 /*
865 * Function prototypes in ixgbe_gld.c
866 */
867 int ixgbe_m_start(void *);
868 void ixgbe_m_stop(void *);
869 int ixgbe_m_promisc(void *, boolean_t);
870 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
871 void ixgbe_m_resources(void *);
872 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
873 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
874 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
875 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
876 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
877 mac_prop_info_handle_t);
878 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
879 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
880 boolean_t ixgbe_param_locked(mac_prop_id_t);
881
882 /*
883 * Function prototypes in ixgbe_rx.c
884 */
885 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
886 void ixgbe_rx_recycle(caddr_t arg);
887 mblk_t *ixgbe_ring_rx_poll(void *, int);
888
889 /*
890 * Function prototypes in ixgbe_tx.c
891 */
892 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
893 void ixgbe_free_tcb(tx_control_block_t *);
894 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
895 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
896 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
897
898 /*
899 * Function prototypes in ixgbe_log.c
900 */
901 void ixgbe_notice(void *, const char *, ...);
902 void ixgbe_log(void *, const char *, ...);
903 void ixgbe_error(void *, const char *, ...);
904
905 /*
906 * Function prototypes in ixgbe_stat.c
907 */
908 int ixgbe_init_stats(ixgbe_t *);
909 int ixgbe_m_stat(void *, uint_t, uint64_t *);
910 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
911 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
912
913 #ifdef __cplusplus
914 }
915 #endif
916
917 #endif /* _IXGBE_SW_H */