1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 */
30
31 #ifndef _IXGBE_SW_H
32 #define _IXGBE_SW_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <sys/types.h>
39 #include <sys/conf.h>
40 #include <sys/debug.h>
41 #include <sys/stropts.h>
42 #include <sys/stream.h>
43 #include <sys/strsun.h>
44 #include <sys/strlog.h>
45 #include <sys/kmem.h>
46 #include <sys/stat.h>
47 #include <sys/kstat.h>
48 #include <sys/modctl.h>
49 #include <sys/errno.h>
50 #include <sys/dlpi.h>
51 #include <sys/mac_provider.h>
52 #include <sys/mac_ether.h>
53 #include <sys/vlan.h>
54 #include <sys/ddi.h>
55 #include <sys/sunddi.h>
56 #include <sys/pci.h>
57 #include <sys/pcie.h>
58 #include <sys/sdt.h>
59 #include <sys/ethernet.h>
60 #include <sys/pattr.h>
61 #include <sys/strsubr.h>
62 #include <sys/netlb.h>
63 #include <sys/random.h>
64 #include <inet/common.h>
65 #include <inet/tcp.h>
66 #include <inet/ip.h>
67 #include <inet/mi.h>
68 #include <inet/nd.h>
69 #include <sys/bitmap.h>
70 #include <sys/ddifm.h>
71 #include <sys/fm/protocol.h>
72 #include <sys/fm/util.h>
73 #include <sys/disp.h>
74 #include <sys/fm/io/ddi.h>
75 #include "ixgbe_api.h"
76
77 #define MODULE_NAME "ixgbe" /* module name */
78
79 #define IXGBE_FAILURE DDI_FAILURE
80
81 #define IXGBE_UNKNOWN 0x00
82 #define IXGBE_INITIALIZED 0x01
83 #define IXGBE_STARTED 0x02
84 #define IXGBE_SUSPENDED 0x04
85 #define IXGBE_STALL 0x08
86 #define IXGBE_OVERTEMP 0x20
87 #define IXGBE_INTR_ADJUST 0x40
88 #define IXGBE_ERROR 0x80
89
90 #define MAX_NUM_UNICAST_ADDRESSES 0x80
91 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
92 #define IXGBE_INTR_NONE 0
93 #define IXGBE_INTR_MSIX 1
94 #define IXGBE_INTR_MSI 2
95 #define IXGBE_INTR_LEGACY 3
96
97 #define IXGBE_POLL_NULL -1
98
99 #define MAX_COOKIE 18
100 #define MIN_NUM_TX_DESC 2
101
102 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
103
104 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
105
106 #define IXGBE_RX_STOPPED 0x1
107
108 #define IXGBE_PKG_BUF_16k 16384
109
110 /*
111 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
112 * supported silicon types.
113 */
114 #define MAX_TX_QUEUE_NUM 128
115 #define MAX_RX_QUEUE_NUM 128
116 #define MAX_INTR_VECTOR 64
117
118 /*
119 * Maximum values for user configurable parameters
120 */
121 #define MAX_TX_RING_SIZE 4096
122 #define MAX_RX_RING_SIZE 4096
123
124 #define MAX_RX_LIMIT_PER_INTR 4096
125
126 #define MAX_RX_COPY_THRESHOLD 9216
127 #define MAX_TX_COPY_THRESHOLD 9216
128 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
129 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
130 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
131
132 /*
133 * Minimum values for user configurable parameters
134 */
135 #define MIN_TX_RING_SIZE 64
136 #define MIN_RX_RING_SIZE 64
137
138 #define MIN_MTU ETHERMIN
139 #define MIN_RX_LIMIT_PER_INTR 16
140 #define MIN_TX_COPY_THRESHOLD 0
141 #define MIN_RX_COPY_THRESHOLD 0
142 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
143 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
144 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
145
146 /*
147 * Default values for user configurable parameters
148 */
149 #define DEFAULT_TX_RING_SIZE 1024
150 #define DEFAULT_RX_RING_SIZE 1024
151
152 #define DEFAULT_MTU ETHERMTU
153 #define DEFAULT_RX_LIMIT_PER_INTR 256
154 #define DEFAULT_RX_COPY_THRESHOLD 128
155 #define DEFAULT_TX_COPY_THRESHOLD 512
156 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
157 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
158 #define DEFAULT_TX_RESCHED_THRESHOLD 128
159 #define DEFAULT_FCRTH 0x20000
160 #define DEFAULT_FCRTL 0x10000
161 #define DEFAULT_FCPAUSE 0xFFFF
162
163 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
164 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
165 #define DEFAULT_LSO_ENABLE B_TRUE
166 #define DEFAULT_LRO_ENABLE B_FALSE
167 #define DEFAULT_MR_ENABLE B_TRUE
168 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
169 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
170 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
171
172 #define IXGBE_LSO_MAXLEN 65535
173
174 #define TX_DRAIN_TIME 200
175 #define RX_DRAIN_TIME 200
176
177 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
178 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
179
180 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
181
182 /*
183 * Extra register bit masks for 82598
184 */
185 #define IXGBE_PCS1GANA_FDC 0x20
186 #define IXGBE_PCS1GANLP_LPFD 0x20
187 #define IXGBE_PCS1GANLP_LPHD 0x40
188
189 /*
190 * Defined for IP header alignment.
191 */
192 #define IPHDR_ALIGN_ROOM 2
193
194 /*
195 * Bit flags for attach_progress
196 */
197 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
198 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
199 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
200 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
201 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
202 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
203 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
204 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
205 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
206 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
207 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
208 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
209 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
210 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
211 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
212
213 #define PROP_DEFAULT_MTU "default_mtu"
214 #define PROP_FLOW_CONTROL "flow_control"
215 #define PROP_TX_QUEUE_NUM "tx_queue_number"
216 #define PROP_TX_RING_SIZE "tx_ring_size"
217 #define PROP_RX_QUEUE_NUM "rx_queue_number"
218 #define PROP_RX_RING_SIZE "rx_ring_size"
219 #define PROP_RX_GROUP_NUM "rx_group_number"
220
221 #define PROP_INTR_FORCE "intr_force"
222 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
223 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
224 #define PROP_LSO_ENABLE "lso_enable"
225 #define PROP_LRO_ENABLE "lro_enable"
226 #define PROP_MR_ENABLE "mr_enable"
227 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
228 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
229 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
230 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
231 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
232 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
233 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
234 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
235 #define PROP_INTR_THROTTLING "intr_throttling"
236 #define PROP_FM_CAPABLE "fm_capable"
237 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
238
239 #define IXGBE_LB_NONE 0
240 #define IXGBE_LB_EXTERNAL 1
241 #define IXGBE_LB_INTERNAL_MAC 2
242 #define IXGBE_LB_INTERNAL_PHY 3
243 #define IXGBE_LB_INTERNAL_SERDES 4
244
245 /*
246 * capability/feature flags
247 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
248 * Separately, the flag named _ENABLED is set when the feature is enabled.
249 */
250 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
251 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
252 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
253 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
254 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
255 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
256 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
257 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
258 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
259 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
260 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
261 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
262
263 /*
264 * Classification mode
265 */
266 #define IXGBE_CLASSIFY_NONE 0
267 #define IXGBE_CLASSIFY_RSS 1
268 #define IXGBE_CLASSIFY_VMDQ 2
269 #define IXGBE_CLASSIFY_VMDQ_RSS 3
270
271 /* adapter-specific info for each supported device type */
272 typedef struct adapter_info {
273 uint32_t max_rx_que_num; /* maximum number of rx queues */
274 uint32_t min_rx_que_num; /* minimum number of rx queues */
275 uint32_t def_rx_que_num; /* default number of rx queues */
276 uint32_t max_rx_grp_num; /* maximum number of rx groups */
277 uint32_t min_rx_grp_num; /* minimum number of rx groups */
278 uint32_t def_rx_grp_num; /* default number of rx groups */
279 uint32_t max_tx_que_num; /* maximum number of tx queues */
280 uint32_t min_tx_que_num; /* minimum number of tx queues */
281 uint32_t def_tx_que_num; /* default number of tx queues */
282 uint32_t max_mtu; /* maximum MTU size */
283 /*
284 * Interrupt throttling is in unit of 256 nsec
285 */
286 uint32_t max_intr_throttle; /* maximum interrupt throttle */
287 uint32_t min_intr_throttle; /* minimum interrupt throttle */
288 uint32_t def_intr_throttle; /* default interrupt throttle */
289
290 uint32_t max_msix_vect; /* maximum total msix vectors */
291 uint32_t max_ring_vect; /* maximum number of ring vectors */
292 uint32_t max_other_vect; /* maximum number of other vectors */
293 uint32_t other_intr; /* "other" interrupt types handled */
294 uint32_t other_gpie; /* "other" interrupt types enabling */
295 uint32_t flags; /* capability flags */
296 } adapter_info_t;
297
298 /* bits representing all interrupt types other than tx & rx */
299 #define IXGBE_OTHER_INTR 0x3ff00000
300 #define IXGBE_82599_OTHER_INTR 0x86100000
301
302 enum ioc_reply {
303 IOC_INVAL = -1, /* bad, NAK with EINVAL */
304 IOC_DONE, /* OK, reply sent */
305 IOC_ACK, /* OK, just send ACK */
306 IOC_REPLY /* OK, just send reply */
307 };
308
309 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
310 0, 0, (flag)))
311
312 /*
313 * Defined for ring index operations
314 * ASSERT(index < limit)
315 * ASSERT(step < limit)
316 * ASSERT(index1 < limit)
317 * ASSERT(index2 < limit)
318 */
319 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
320 (index) + (step) : (index) + (step) - (limit))
321 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
322 (index) - (step) : (index) + (limit) - (step))
323 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
324 (index2) - (index1) : (index2) + (limit) - (index1))
325
326 #define LINK_LIST_INIT(_LH) \
327 (_LH)->head = (_LH)->tail = NULL
328
329 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
330
331 #define LIST_POP_HEAD(_LH) \
332 (single_link_t *)(_LH)->head; \
333 { \
334 if ((_LH)->head != NULL) { \
335 (_LH)->head = (_LH)->head->link; \
336 if ((_LH)->head == NULL) \
337 (_LH)->tail = NULL; \
338 } \
339 }
340
341 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
342
343 #define LIST_PUSH_TAIL(_LH, _E) \
344 if ((_LH)->tail != NULL) { \
345 (_LH)->tail->link = (single_link_t *)(_E); \
346 (_LH)->tail = (single_link_t *)(_E); \
347 } else { \
348 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
349 } \
350 (_E)->link = NULL;
351
352 #define LIST_GET_NEXT(_LH, _E) \
353 (((_LH)->tail == (single_link_t *)(_E)) ? \
354 NULL : ((single_link_t *)(_E))->link)
355
356
357 typedef struct single_link {
358 struct single_link *link;
359 } single_link_t;
360
361 typedef struct link_list {
362 single_link_t *head;
363 single_link_t *tail;
364 } link_list_t;
365
366 /*
367 * Property lookups
368 */
369 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
370 DDI_PROP_DONTPASS, (n))
371 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
372 DDI_PROP_DONTPASS, (n), -1)
373
374
375 typedef union ixgbe_ether_addr {
376 struct {
377 uint32_t high;
378 uint32_t low;
379 } reg;
380 struct {
381 uint8_t set;
382 uint8_t group_index;
383 uint8_t addr[ETHERADDRL];
384 } mac;
385 } ixgbe_ether_addr_t;
386
387 typedef enum {
388 USE_NONE,
389 USE_COPY,
390 USE_DMA
391 } tx_type_t;
392
393 typedef struct ixgbe_tx_context {
394 uint32_t hcksum_flags;
395 uint32_t ip_hdr_len;
396 uint32_t mac_hdr_len;
397 uint32_t l4_proto;
398 uint32_t mss;
399 uint32_t l4_hdr_len;
400 boolean_t lso_flag;
401 } ixgbe_tx_context_t;
402
403 /*
404 * Hold address/length of each DMA segment
405 */
406 typedef struct sw_desc {
407 uint64_t address;
408 size_t length;
409 } sw_desc_t;
410
411 /*
412 * Handles and addresses of DMA buffer
413 */
414 typedef struct dma_buffer {
415 caddr_t address; /* Virtual address */
416 uint64_t dma_address; /* DMA (Hardware) address */
417 ddi_acc_handle_t acc_handle; /* Data access handle */
418 ddi_dma_handle_t dma_handle; /* DMA handle */
419 size_t size; /* Buffer size */
420 size_t len; /* Data length in the buffer */
421 } dma_buffer_t;
422
423 /*
424 * Tx Control Block
425 */
426 typedef struct tx_control_block {
427 single_link_t link;
428 uint32_t last_index; /* last descriptor of the pkt */
429 uint32_t frag_num;
430 uint32_t desc_num;
431 mblk_t *mp;
432 tx_type_t tx_type;
433 ddi_dma_handle_t tx_dma_handle;
434 dma_buffer_t tx_buf;
435 sw_desc_t desc[MAX_COOKIE];
436 } tx_control_block_t;
437
438 /*
439 * RX Control Block
440 */
441 typedef struct rx_control_block {
442 mblk_t *mp;
443 uint32_t ref_cnt;
444 dma_buffer_t rx_buf;
445 frtn_t free_rtn;
446 struct ixgbe_rx_data *rx_data;
447 int lro_next; /* Index of next rcb */
448 int lro_prev; /* Index of previous rcb */
449 boolean_t lro_pkt; /* Flag for LRO rcb */
450 } rx_control_block_t;
451
452 /*
453 * Software Data Structure for Tx Ring
454 */
455 typedef struct ixgbe_tx_ring {
456 uint32_t index; /* Ring index */
457 uint32_t intr_vector; /* Interrupt vector index */
458 uint32_t vect_bit; /* vector's bit in register */
459
460 /*
461 * Mutexes
462 */
463 kmutex_t tx_lock;
464 kmutex_t recycle_lock;
465 kmutex_t tcb_head_lock;
466 kmutex_t tcb_tail_lock;
467
468 /*
469 * Tx descriptor ring definitions
470 */
471 dma_buffer_t tbd_area;
472 union ixgbe_adv_tx_desc *tbd_ring;
473 uint32_t tbd_head; /* Index of next tbd to recycle */
474 uint32_t tbd_tail; /* Index of next tbd to transmit */
475 uint32_t tbd_free; /* Number of free tbd */
476
477 /*
478 * Tx control block list definitions
479 */
480 tx_control_block_t *tcb_area;
481 tx_control_block_t **work_list;
482 tx_control_block_t **free_list;
483 uint32_t tcb_head; /* Head index of free list */
484 uint32_t tcb_tail; /* Tail index of free list */
485 uint32_t tcb_free; /* Number of free tcb in free list */
486
487 uint32_t *tbd_head_wb; /* Head write-back */
488 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *);
489
490 /*
491 * s/w context structure for TCP/UDP checksum offload
492 * and LSO.
493 */
494 ixgbe_tx_context_t tx_context;
495
496 /*
497 * Tx ring settings and status
498 */
499 uint32_t ring_size; /* Tx descriptor ring size */
500 uint32_t free_list_size; /* Tx free list size */
501
502 boolean_t reschedule;
503 uint32_t recycle_fail;
504 uint32_t stall_watchdog;
505
506 #ifdef IXGBE_DEBUG
507 /*
508 * Debug statistics
509 */
510 uint32_t stat_overload;
511 uint32_t stat_fail_no_tbd;
512 uint32_t stat_fail_no_tcb;
513 uint32_t stat_fail_dma_bind;
514 uint32_t stat_reschedule;
515 uint32_t stat_break_tbd_limit;
516 uint32_t stat_lso_header_fail;
517 #endif
518 uint64_t stat_obytes;
519 uint64_t stat_opackets;
520
521 mac_ring_handle_t ring_handle;
522
523 /*
524 * Pointer to the ixgbe struct
525 */
526 struct ixgbe *ixgbe;
527 } ixgbe_tx_ring_t;
528
529 /*
530 * Software Receive Ring
531 */
532 typedef struct ixgbe_rx_data {
533 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
534
535 /*
536 * Rx descriptor ring definitions
537 */
538 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
539 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */
540 uint32_t rbd_next; /* Index of next rx desc */
541
542 /*
543 * Rx control block list definitions
544 */
545 rx_control_block_t *rcb_area;
546 rx_control_block_t **work_list; /* Work list of rcbs */
547 rx_control_block_t **free_list; /* Free list of rcbs */
548 uint32_t rcb_head; /* Index of next free rcb */
549 uint32_t rcb_tail; /* Index to put recycled rcb */
550 uint32_t rcb_free; /* Number of free rcbs */
551
552 /*
553 * Rx sw ring settings and status
554 */
555 uint32_t ring_size; /* Rx descriptor ring size */
556 uint32_t free_list_size; /* Rx free list size */
557
558 uint32_t rcb_pending;
559 uint32_t flag;
560
561 uint32_t lro_num; /* Number of rcbs of one LRO */
562 uint32_t lro_first; /* Index of first LRO rcb */
563
564 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */
565 } ixgbe_rx_data_t;
566
567 /*
568 * Software Data Structure for Rx Ring
569 */
570 typedef struct ixgbe_rx_ring {
571 uint32_t index; /* Ring index */
572 uint32_t group_index; /* Group index */
573 uint32_t hw_index; /* h/w ring index */
574 uint32_t intr_vector; /* Interrupt vector index */
575 uint32_t vect_bit; /* vector's bit in register */
576
577 ixgbe_rx_data_t *rx_data; /* Rx software ring */
578
579 kmutex_t rx_lock; /* Rx access lock */
580
581 #ifdef IXGBE_DEBUG
582 /*
583 * Debug statistics
584 */
585 uint32_t stat_frame_error;
586 uint32_t stat_cksum_error;
587 uint32_t stat_exceed_pkt;
588 #endif
589 uint64_t stat_rbytes;
590 uint64_t stat_ipackets;
591
592 mac_ring_handle_t ring_handle;
593 uint64_t ring_gen_num;
594
595 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
596 } ixgbe_rx_ring_t;
597 /*
598 * Software Receive Ring Group
599 */
600 typedef struct ixgbe_rx_group {
601 uint32_t index; /* Group index */
602 mac_group_handle_t group_handle; /* call back group handle */
603 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
604 } ixgbe_rx_group_t;
605
606 /*
607 * structure to map interrupt cleanup to msi-x vector
608 */
609 typedef struct ixgbe_intr_vector {
610 struct ixgbe *ixgbe; /* point to my adapter */
611 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
612 int rxr_cnt; /* count rx rings */
613 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
614 int txr_cnt; /* count tx rings */
615 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
616 int other_cnt; /* count other interrupt */
617 } ixgbe_intr_vector_t;
618
619 /*
620 * Software adapter state
621 */
622 typedef struct ixgbe {
623 int instance;
624 mac_handle_t mac_hdl;
625 dev_info_t *dip;
626 struct ixgbe_hw hw;
627 struct ixgbe_osdep osdep;
628
629 adapter_info_t *capab; /* adapter hardware capabilities */
630 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
631 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
632 uint32_t eims; /* interrupt mask setting */
633 uint32_t eimc; /* interrupt mask clear */
634 uint32_t eicr; /* interrupt cause reg */
635
636 uint32_t ixgbe_state;
637 link_state_t link_state;
638 uint32_t link_speed;
639 uint32_t link_duplex;
640
641 uint32_t reset_count;
642 uint32_t attach_progress;
643 uint32_t loopback_mode;
644 uint32_t default_mtu;
645 uint32_t max_frame_size;
646
647 uint32_t rcb_pending;
648
649 /*
650 * Each msi-x vector: map vector to interrupt cleanup
651 */
652 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
653
654 /*
655 * Receive Rings
656 */
657 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
658 uint32_t num_rx_rings; /* Number of rx rings in use */
659 uint32_t rx_ring_size; /* Rx descriptor ring size */
660 uint32_t rx_buf_size; /* Rx buffer size */
661 boolean_t lro_enable; /* Large Receive Offload */
662 uint64_t lro_pkt_count; /* LRO packet count */
663 /*
664 * Receive Groups
665 */
666 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
667 uint32_t num_rx_groups; /* Number of rx groups in use */
668
669 /*
670 * Transmit Rings
671 */
672 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
673 uint32_t num_tx_rings; /* Number of tx rings in use */
674 uint32_t tx_ring_size; /* Tx descriptor ring size */
675 uint32_t tx_buf_size; /* Tx buffer size */
676
677 boolean_t tx_ring_init;
678 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
679 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
680 boolean_t lso_enable; /* Large Segment Offload */
681 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
682 boolean_t relax_order_enable; /* Relax Order */
683 uint32_t classify_mode; /* Classification mode */
684 uint32_t tx_copy_thresh; /* Tx copy threshold */
685 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
686 uint32_t tx_overload_thresh; /* Tx overload threshold */
687 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
688 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
689 uint32_t rx_copy_thresh; /* Rx copy threshold */
690 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
691 uint32_t intr_throttling[MAX_INTR_VECTOR];
692 uint32_t intr_force;
693 int fm_capabilities; /* FMA capabilities */
694
695 int intr_type;
696 int intr_cnt;
697 uint32_t intr_cnt_max;
698 uint32_t intr_cnt_min;
699 int intr_cap;
700 size_t intr_size;
701 uint_t intr_pri;
702 ddi_intr_handle_t *htable;
703 uint32_t eims_mask;
704 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
705
706 kmutex_t gen_lock; /* General lock for device access */
707 kmutex_t watchdog_lock;
708 kmutex_t rx_pending_lock;
709
710 boolean_t watchdog_enable;
711 boolean_t watchdog_start;
712 timeout_id_t watchdog_tid;
713
714 boolean_t unicst_init;
715 uint32_t unicst_avail;
716 uint32_t unicst_total;
717 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
718 uint32_t mcast_count;
719 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
720
721 ulong_t sys_page_size;
722
723 boolean_t link_check_complete;
724 hrtime_t link_check_hrtime;
725 ddi_periodic_t periodic_id; /* for link check timer func */
726
727 /*
728 * Kstat definitions
729 */
730 kstat_t *ixgbe_ks;
731
732 uint32_t param_en_10000fdx_cap:1,
733 param_en_1000fdx_cap:1,
734 param_en_100fdx_cap:1,
735 param_adv_10000fdx_cap:1,
736 param_adv_1000fdx_cap:1,
737 param_adv_100fdx_cap:1,
738 param_pause_cap:1,
739 param_asym_pause_cap:1,
740 param_rem_fault:1,
741 param_adv_autoneg_cap:1,
742 param_adv_pause_cap:1,
743 param_adv_asym_pause_cap:1,
744 param_adv_rem_fault:1,
745 param_lp_10000fdx_cap:1,
746 param_lp_1000fdx_cap:1,
747 param_lp_100fdx_cap:1,
748 param_lp_autoneg_cap:1,
749 param_lp_pause_cap:1,
750 param_lp_asym_pause_cap:1,
751 param_lp_rem_fault:1,
752 param_pad_to_32:12;
753 } ixgbe_t;
754
755 typedef struct ixgbe_stat {
756 kstat_named_t link_speed; /* Link Speed */
757
758 kstat_named_t reset_count; /* Reset Count */
759
760 kstat_named_t rx_frame_error; /* Rx Error in Packet */
761 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
762 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
763
764 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
765 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
766 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
767 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
768 kstat_named_t tx_reschedule; /* Tx Reschedule */
769
770 kstat_named_t gprc; /* Good Packets Received Count */
771 kstat_named_t gptc; /* Good Packets Xmitted Count */
772 kstat_named_t gor; /* Good Octets Received Count */
773 kstat_named_t got; /* Good Octets Xmitd Count */
774 kstat_named_t prc64; /* Packets Received - 64b */
775 kstat_named_t prc127; /* Packets Received - 65-127b */
776 kstat_named_t prc255; /* Packets Received - 127-255b */
777 kstat_named_t prc511; /* Packets Received - 256-511b */
778 kstat_named_t prc1023; /* Packets Received - 511-1023b */
779 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
780 kstat_named_t ptc64; /* Packets Xmitted (64b) */
781 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
782 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
783 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
784 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
785 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
786 kstat_named_t qprc[16]; /* Queue Packets Received Count */
787 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */
788 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */
789 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */
790
791 kstat_named_t crcerrs; /* CRC Error Count */
792 kstat_named_t illerrc; /* Illegal Byte Error Count */
793 kstat_named_t errbc; /* Error Byte Count */
794 kstat_named_t mspdc; /* MAC Short Packet Discard Count */
795 kstat_named_t mpc; /* Missed Packets Count */
796 kstat_named_t mlfc; /* MAC Local Fault Count */
797 kstat_named_t mrfc; /* MAC Remote Fault Count */
798 kstat_named_t rlec; /* Receive Length Error Count */
799 kstat_named_t lxontxc; /* Link XON Transmitted Count */
800 kstat_named_t lxonrxc; /* Link XON Received Count */
801 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
802 kstat_named_t lxoffrxc; /* Link XOFF Received Count */
803 kstat_named_t bprc; /* Broadcasts Pkts Received Count */
804 kstat_named_t mprc; /* Multicast Pkts Received Count */
805 kstat_named_t rnbc; /* Receive No Buffers Count */
806 kstat_named_t ruc; /* Receive Undersize Count */
807 kstat_named_t rfc; /* Receive Frag Count */
808 kstat_named_t roc; /* Receive Oversize Count */
809 kstat_named_t rjc; /* Receive Jabber Count */
810 kstat_named_t tor; /* Total Octets Recvd Count */
811 kstat_named_t tot; /* Total Octets Xmitted Count */
812 kstat_named_t tpr; /* Total Packets Received */
813 kstat_named_t tpt; /* Total Packets Xmitted */
814 kstat_named_t mptc; /* Multicast Packets Xmited Count */
815 kstat_named_t bptc; /* Broadcast Packets Xmited Count */
816 kstat_named_t lroc; /* LRO Packets Received Count */
817 } ixgbe_stat_t;
818
819 /*
820 * Function prototypes in ixgbe_buf.c
821 */
822 int ixgbe_alloc_dma(ixgbe_t *);
823 void ixgbe_free_dma(ixgbe_t *);
824 void ixgbe_set_fma_flags(int);
825 void ixgbe_free_dma_buffer(dma_buffer_t *);
826 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
827 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
828
829 /*
830 * Function prototypes in ixgbe_main.c
831 */
832 int ixgbe_start(ixgbe_t *, boolean_t);
833 void ixgbe_stop(ixgbe_t *, boolean_t);
834 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
835 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
836 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
837 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
838
839 void ixgbe_enable_watchdog_timer(ixgbe_t *);
840 void ixgbe_disable_watchdog_timer(ixgbe_t *);
841 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
842
843 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
844 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
845 void ixgbe_fm_ereport(ixgbe_t *, char *);
846
847 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
848 mac_ring_info_t *, mac_ring_handle_t);
849 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
850 mac_group_info_t *, mac_group_handle_t);
851 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
852 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
853
854 /*
855 * Function prototypes in ixgbe_gld.c
856 */
857 int ixgbe_m_start(void *);
858 void ixgbe_m_stop(void *);
859 int ixgbe_m_promisc(void *, boolean_t);
860 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
861 void ixgbe_m_resources(void *);
862 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
863 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
864 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
865 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
866 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
867 mac_prop_info_handle_t);
868 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
869 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
870 boolean_t ixgbe_param_locked(mac_prop_id_t);
871
872 /*
873 * Function prototypes in ixgbe_rx.c
874 */
875 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
876 void ixgbe_rx_recycle(caddr_t arg);
877 mblk_t *ixgbe_ring_rx_poll(void *, int);
878
879 /*
880 * Function prototypes in ixgbe_tx.c
881 */
882 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
883 void ixgbe_free_tcb(tx_control_block_t *);
884 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
885 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
886 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
887
888 /*
889 * Function prototypes in ixgbe_log.c
890 */
891 void ixgbe_notice(void *, const char *, ...);
892 void ixgbe_log(void *, const char *, ...);
893 void ixgbe_error(void *, const char *, ...);
894
895 /*
896 * Function prototypes in ixgbe_stat.c
897 */
898 int ixgbe_init_stats(ixgbe_t *);
899 int ixgbe_m_stat(void *, uint_t, uint64_t *);
900 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
901 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
902
903 #ifdef __cplusplus
904 }
905 #endif
906
907 #endif /* _IXGBE_SW_H */