9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29 */
30
31 #include "ixgbe_sw.h"
32
33 /*
34 * Update driver private statistics.
35 */
36 static int
37 ixgbe_update_stats(kstat_t *ks, int rw)
38 {
39 ixgbe_t *ixgbe;
40 struct ixgbe_hw *hw;
41 ixgbe_stat_t *ixgbe_ks;
42 int i;
43
44 if (rw == KSTAT_WRITE)
45 return (EACCES);
46
47 ixgbe = (ixgbe_t *)ks->ks_private;
48 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
97 ixgbe_ks->tor.value.ui64 = 0;
98 ixgbe_ks->tot.value.ui64 = 0;
99 for (i = 0; i < 16; i++) {
100 ixgbe_ks->qprc[i].value.ui64 +=
101 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
102 ixgbe_ks->gprc.value.ui64 += ixgbe_ks->qprc[i].value.ui64;
103 ixgbe_ks->qptc[i].value.ui64 +=
104 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
105 ixgbe_ks->gptc.value.ui64 += ixgbe_ks->qptc[i].value.ui64;
106 ixgbe_ks->qbrc[i].value.ui64 +=
107 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
108 ixgbe_ks->tor.value.ui64 += ixgbe_ks->qbrc[i].value.ui64;
109 switch (hw->mac.type) {
110 case ixgbe_mac_82598EB:
111 ixgbe_ks->qbtc[i].value.ui64 +=
112 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
113 break;
114
115 case ixgbe_mac_82599EB:
116 case ixgbe_mac_X540:
117 ixgbe_ks->qbtc[i].value.ui64 +=
118 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
119 ixgbe_ks->qbtc[i].value.ui64 +=
120 ((uint64_t)((IXGBE_READ_REG(hw,
121 IXGBE_QBTC_H(i))) & 0xF) << 32);
122 break;
123
124 default:
125 break;
126 }
127 ixgbe_ks->tot.value.ui64 += ixgbe_ks->qbtc[i].value.ui64;
128 }
129 /*
130 * This is a Workaround:
131 * Currently h/w GORCH, GOTCH, TORH registers are not
132 * correctly implemented. We found that the values in
133 * these registers are same as those in corresponding
134 * *L registers (i.e. GORCL, GOTCL, and TORL). Here the
135 * gor and got stat data will not be retrieved through
136 * GORC{H/L} and GOTC{H/L} registers but be obtained by
151 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
152 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
153 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
154 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
155
156 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
157 for (i = 0; i < 8; i++)
158 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
159 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
160 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
161 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
162 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
163 switch (hw->mac.type) {
164 case ixgbe_mac_82598EB:
165 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
166 IXGBE_LXONRXC);
167 break;
168
169 case ixgbe_mac_82599EB:
170 case ixgbe_mac_X540:
171 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
172 IXGBE_LXONRXCNT);
173 break;
174
175 default:
176 break;
177 }
178 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
179 switch (hw->mac.type) {
180 case ixgbe_mac_82598EB:
181 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
182 IXGBE_LXOFFRXC);
183 break;
184
185 case ixgbe_mac_82599EB:
186 case ixgbe_mac_X540:
187 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
188 IXGBE_LXOFFRXCNT);
189 break;
190
191 default:
192 break;
193 }
194 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
195 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
196 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
197 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
198
199 mutex_exit(&ixgbe->gen_lock);
200
201 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
202 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
203
204 return (0);
205 }
206
460 ks->ks_private = (void *)ixgbe;
461
462 /*
463 * Add kstat to systems kstat chain
464 */
465 kstat_install(ks);
466
467 return (IXGBE_SUCCESS);
468 }
469
470 /*
471 * Retrieve a value for one of the statistics.
472 */
473 int
474 ixgbe_m_stat(void *arg, uint_t stat, uint64_t *val)
475 {
476 ixgbe_t *ixgbe = (ixgbe_t *)arg;
477 struct ixgbe_hw *hw = &ixgbe->hw;
478 ixgbe_stat_t *ixgbe_ks;
479 int i;
480
481 ixgbe_ks = (ixgbe_stat_t *)ixgbe->ixgbe_ks->ks_data;
482
483 mutex_enter(&ixgbe->gen_lock);
484
485 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
486 mutex_exit(&ixgbe->gen_lock);
487 return (ECANCELED);
488 }
489
490 switch (stat) {
491 case MAC_STAT_IFSPEED:
492 *val = ixgbe->link_speed * 1000000ull;
493 break;
494
495 case MAC_STAT_MULTIRCV:
496 ixgbe_ks->mprc.value.ui64 +=
497 IXGBE_READ_REG(hw, IXGBE_MPRC);
498 *val = ixgbe_ks->mprc.value.ui64;
499 break;
500
501 case MAC_STAT_BRDCSTRCV:
502 ixgbe_ks->bprc.value.ui64 +=
503 IXGBE_READ_REG(hw, IXGBE_BPRC);
504 *val = ixgbe_ks->bprc.value.ui64;
544 for (i = 0; i < 16; i++) {
545 ixgbe_ks->qbrc[i].value.ui64 +=
546 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
547 ixgbe_ks->tor.value.ui64 +=
548 ixgbe_ks->qbrc[i].value.ui64;
549 }
550 *val = ixgbe_ks->tor.value.ui64;
551 break;
552
553 case MAC_STAT_OBYTES:
554 ixgbe_ks->tot.value.ui64 = 0;
555 for (i = 0; i < 16; i++) {
556 switch (hw->mac.type) {
557 case ixgbe_mac_82598EB:
558 ixgbe_ks->qbtc[i].value.ui64 +=
559 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
560 break;
561
562 case ixgbe_mac_82599EB:
563 case ixgbe_mac_X540:
564 ixgbe_ks->qbtc[i].value.ui64 +=
565 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
566 ixgbe_ks->qbtc[i].value.ui64 +=
567 ((uint64_t)((IXGBE_READ_REG(hw,
568 IXGBE_QBTC_H(i))) & 0xF) << 32);
569 break;
570
571 default:
572 break;
573 }
574 ixgbe_ks->tot.value.ui64 +=
575 ixgbe_ks->qbtc[i].value.ui64;
576 }
577 *val = ixgbe_ks->tot.value.ui64;
578 break;
579
580 case MAC_STAT_IPACKETS:
581 ixgbe_ks->tpr.value.ui64 +=
582 IXGBE_READ_REG(hw, IXGBE_TPR);
583 *val = ixgbe_ks->tpr.value.ui64;
628 break;
629
630 case ETHER_STAT_XCVR_INUSE:
631 switch (ixgbe->link_speed) {
632 case IXGBE_LINK_SPEED_1GB_FULL:
633 *val =
634 (hw->phy.media_type == ixgbe_media_type_copper) ?
635 XCVR_1000T : XCVR_1000X;
636 break;
637 case IXGBE_LINK_SPEED_100_FULL:
638 *val = (hw->phy.media_type == ixgbe_media_type_copper) ?
639 XCVR_100T2 : XCVR_100X;
640 break;
641 default:
642 *val = XCVR_NONE;
643 break;
644 }
645 break;
646
647 case ETHER_STAT_CAP_10GFDX:
648 *val = 1;
649 break;
650
651 case ETHER_STAT_CAP_1000FDX:
652 *val = 1;
653 break;
654
655 case ETHER_STAT_CAP_100FDX:
656 *val = 1;
657 break;
658
659 case ETHER_STAT_CAP_ASMPAUSE:
660 *val = ixgbe->param_asym_pause_cap;
661 break;
662
663 case ETHER_STAT_CAP_PAUSE:
664 *val = ixgbe->param_pause_cap;
665 break;
666
667 case ETHER_STAT_CAP_AUTONEG:
668 *val = 1;
669 break;
670
671 case ETHER_STAT_ADV_CAP_10GFDX:
672 *val = ixgbe->param_adv_10000fdx_cap;
673 break;
674
675 case ETHER_STAT_ADV_CAP_1000FDX:
676 *val = ixgbe->param_adv_1000fdx_cap;
677 break;
678
679 case ETHER_STAT_ADV_CAP_100FDX:
680 *val = ixgbe->param_adv_100fdx_cap;
681 break;
682
683 case ETHER_STAT_ADV_CAP_ASMPAUSE:
684 *val = ixgbe->param_adv_asym_pause_cap;
685 break;
686
687 case ETHER_STAT_ADV_CAP_PAUSE:
688 *val = ixgbe->param_adv_pause_cap;
689 break;
690
691 case ETHER_STAT_ADV_CAP_AUTONEG:
692 *val = ixgbe->param_adv_autoneg_cap;
693 break;
694
695 case ETHER_STAT_LP_CAP_10GFDX:
696 *val = ixgbe->param_lp_10000fdx_cap;
697 break;
698
699 case ETHER_STAT_LP_CAP_1000FDX:
700 *val = ixgbe->param_lp_1000fdx_cap;
701 break;
702
703 case ETHER_STAT_LP_CAP_100FDX:
704 *val = ixgbe->param_lp_100fdx_cap;
705 break;
706
707 case ETHER_STAT_LP_CAP_ASMPAUSE:
708 *val = ixgbe->param_lp_asym_pause_cap;
709 break;
710
711 case ETHER_STAT_LP_CAP_PAUSE:
712 *val = ixgbe->param_lp_pause_cap;
713 break;
714
715 case ETHER_STAT_LP_CAP_AUTONEG:
716 *val = ixgbe->param_lp_autoneg_cap;
717 break;
718
|
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 */
31
32 #include "ixgbe_sw.h"
33
34 /*
35 * Update driver private statistics.
36 */
37 static int
38 ixgbe_update_stats(kstat_t *ks, int rw)
39 {
40 ixgbe_t *ixgbe;
41 struct ixgbe_hw *hw;
42 ixgbe_stat_t *ixgbe_ks;
43 int i;
44
45 if (rw == KSTAT_WRITE)
46 return (EACCES);
47
48 ixgbe = (ixgbe_t *)ks->ks_private;
49 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
98 ixgbe_ks->tor.value.ui64 = 0;
99 ixgbe_ks->tot.value.ui64 = 0;
100 for (i = 0; i < 16; i++) {
101 ixgbe_ks->qprc[i].value.ui64 +=
102 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
103 ixgbe_ks->gprc.value.ui64 += ixgbe_ks->qprc[i].value.ui64;
104 ixgbe_ks->qptc[i].value.ui64 +=
105 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
106 ixgbe_ks->gptc.value.ui64 += ixgbe_ks->qptc[i].value.ui64;
107 ixgbe_ks->qbrc[i].value.ui64 +=
108 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
109 ixgbe_ks->tor.value.ui64 += ixgbe_ks->qbrc[i].value.ui64;
110 switch (hw->mac.type) {
111 case ixgbe_mac_82598EB:
112 ixgbe_ks->qbtc[i].value.ui64 +=
113 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
114 break;
115
116 case ixgbe_mac_82599EB:
117 case ixgbe_mac_X540:
118 case ixgbe_mac_X550:
119 case ixgbe_mac_X550EM_x:
120 ixgbe_ks->qbtc[i].value.ui64 +=
121 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
122 ixgbe_ks->qbtc[i].value.ui64 +=
123 ((uint64_t)((IXGBE_READ_REG(hw,
124 IXGBE_QBTC_H(i))) & 0xF) << 32);
125 break;
126
127 default:
128 break;
129 }
130 ixgbe_ks->tot.value.ui64 += ixgbe_ks->qbtc[i].value.ui64;
131 }
132 /*
133 * This is a Workaround:
134 * Currently h/w GORCH, GOTCH, TORH registers are not
135 * correctly implemented. We found that the values in
136 * these registers are same as those in corresponding
137 * *L registers (i.e. GORCL, GOTCL, and TORL). Here the
138 * gor and got stat data will not be retrieved through
139 * GORC{H/L} and GOTC{H/L} registers but be obtained by
154 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
155 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
156 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
157 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
158
159 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
160 for (i = 0; i < 8; i++)
161 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
162 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
163 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
164 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
165 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
166 switch (hw->mac.type) {
167 case ixgbe_mac_82598EB:
168 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
169 IXGBE_LXONRXC);
170 break;
171
172 case ixgbe_mac_82599EB:
173 case ixgbe_mac_X540:
174 case ixgbe_mac_X550:
175 case ixgbe_mac_X550EM_x:
176 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
177 IXGBE_LXONRXCNT);
178 break;
179
180 default:
181 break;
182 }
183 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
184 switch (hw->mac.type) {
185 case ixgbe_mac_82598EB:
186 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
187 IXGBE_LXOFFRXC);
188 break;
189
190 case ixgbe_mac_82599EB:
191 case ixgbe_mac_X540:
192 case ixgbe_mac_X550:
193 case ixgbe_mac_X550EM_x:
194 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
195 IXGBE_LXOFFRXCNT);
196 break;
197
198 default:
199 break;
200 }
201 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
202 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
203 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
204 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
205
206 mutex_exit(&ixgbe->gen_lock);
207
208 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
209 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
210
211 return (0);
212 }
213
467 ks->ks_private = (void *)ixgbe;
468
469 /*
470 * Add kstat to systems kstat chain
471 */
472 kstat_install(ks);
473
474 return (IXGBE_SUCCESS);
475 }
476
477 /*
478 * Retrieve a value for one of the statistics.
479 */
480 int
481 ixgbe_m_stat(void *arg, uint_t stat, uint64_t *val)
482 {
483 ixgbe_t *ixgbe = (ixgbe_t *)arg;
484 struct ixgbe_hw *hw = &ixgbe->hw;
485 ixgbe_stat_t *ixgbe_ks;
486 int i;
487 ixgbe_link_speed speeds = 0;
488
489 ixgbe_ks = (ixgbe_stat_t *)ixgbe->ixgbe_ks->ks_data;
490
491 mutex_enter(&ixgbe->gen_lock);
492
493 /*
494 * We cannot always rely on the common code maintaining
495 * hw->phy.speeds_supported, therefore we fall back to use the recorded
496 * supported speeds which were obtained during instance init in
497 * ixgbe_init_params().
498 */
499 speeds = hw->phy.speeds_supported;
500 if (speeds == 0)
501 speeds = ixgbe->speeds_supported;
502
503 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
504 mutex_exit(&ixgbe->gen_lock);
505 return (ECANCELED);
506 }
507
508 switch (stat) {
509 case MAC_STAT_IFSPEED:
510 *val = ixgbe->link_speed * 1000000ull;
511 break;
512
513 case MAC_STAT_MULTIRCV:
514 ixgbe_ks->mprc.value.ui64 +=
515 IXGBE_READ_REG(hw, IXGBE_MPRC);
516 *val = ixgbe_ks->mprc.value.ui64;
517 break;
518
519 case MAC_STAT_BRDCSTRCV:
520 ixgbe_ks->bprc.value.ui64 +=
521 IXGBE_READ_REG(hw, IXGBE_BPRC);
522 *val = ixgbe_ks->bprc.value.ui64;
562 for (i = 0; i < 16; i++) {
563 ixgbe_ks->qbrc[i].value.ui64 +=
564 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
565 ixgbe_ks->tor.value.ui64 +=
566 ixgbe_ks->qbrc[i].value.ui64;
567 }
568 *val = ixgbe_ks->tor.value.ui64;
569 break;
570
571 case MAC_STAT_OBYTES:
572 ixgbe_ks->tot.value.ui64 = 0;
573 for (i = 0; i < 16; i++) {
574 switch (hw->mac.type) {
575 case ixgbe_mac_82598EB:
576 ixgbe_ks->qbtc[i].value.ui64 +=
577 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
578 break;
579
580 case ixgbe_mac_82599EB:
581 case ixgbe_mac_X540:
582 case ixgbe_mac_X550:
583 case ixgbe_mac_X550EM_x:
584 ixgbe_ks->qbtc[i].value.ui64 +=
585 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
586 ixgbe_ks->qbtc[i].value.ui64 +=
587 ((uint64_t)((IXGBE_READ_REG(hw,
588 IXGBE_QBTC_H(i))) & 0xF) << 32);
589 break;
590
591 default:
592 break;
593 }
594 ixgbe_ks->tot.value.ui64 +=
595 ixgbe_ks->qbtc[i].value.ui64;
596 }
597 *val = ixgbe_ks->tot.value.ui64;
598 break;
599
600 case MAC_STAT_IPACKETS:
601 ixgbe_ks->tpr.value.ui64 +=
602 IXGBE_READ_REG(hw, IXGBE_TPR);
603 *val = ixgbe_ks->tpr.value.ui64;
648 break;
649
650 case ETHER_STAT_XCVR_INUSE:
651 switch (ixgbe->link_speed) {
652 case IXGBE_LINK_SPEED_1GB_FULL:
653 *val =
654 (hw->phy.media_type == ixgbe_media_type_copper) ?
655 XCVR_1000T : XCVR_1000X;
656 break;
657 case IXGBE_LINK_SPEED_100_FULL:
658 *val = (hw->phy.media_type == ixgbe_media_type_copper) ?
659 XCVR_100T2 : XCVR_100X;
660 break;
661 default:
662 *val = XCVR_NONE;
663 break;
664 }
665 break;
666
667 case ETHER_STAT_CAP_10GFDX:
668 *val = (speeds & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
669 break;
670
671 case ETHER_STAT_CAP_5000FDX:
672 *val = (speeds & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
673 break;
674
675 case ETHER_STAT_CAP_2500FDX:
676 *val = (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
677 break;
678
679 case ETHER_STAT_CAP_1000FDX:
680 *val = (speeds & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
681 break;
682
683 case ETHER_STAT_CAP_100FDX:
684 *val = (speeds & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
685 break;
686
687 case ETHER_STAT_CAP_ASMPAUSE:
688 *val = ixgbe->param_asym_pause_cap;
689 break;
690
691 case ETHER_STAT_CAP_PAUSE:
692 *val = ixgbe->param_pause_cap;
693 break;
694
695 case ETHER_STAT_CAP_AUTONEG:
696 *val = 1;
697 break;
698
699 case ETHER_STAT_ADV_CAP_10GFDX:
700 *val = ixgbe->param_adv_10000fdx_cap;
701 break;
702
703 case ETHER_STAT_ADV_CAP_5000FDX:
704 *val = ixgbe->param_adv_5000fdx_cap;
705 break;
706
707 case ETHER_STAT_ADV_CAP_2500FDX:
708 *val = ixgbe->param_adv_2500fdx_cap;
709 break;
710
711 case ETHER_STAT_ADV_CAP_1000FDX:
712 *val = ixgbe->param_adv_1000fdx_cap;
713 break;
714
715 case ETHER_STAT_ADV_CAP_100FDX:
716 *val = ixgbe->param_adv_100fdx_cap;
717 break;
718
719 case ETHER_STAT_ADV_CAP_ASMPAUSE:
720 *val = ixgbe->param_adv_asym_pause_cap;
721 break;
722
723 case ETHER_STAT_ADV_CAP_PAUSE:
724 *val = ixgbe->param_adv_pause_cap;
725 break;
726
727 case ETHER_STAT_ADV_CAP_AUTONEG:
728 *val = ixgbe->param_adv_autoneg_cap;
729 break;
730
731 case ETHER_STAT_LP_CAP_10GFDX:
732 *val = ixgbe->param_lp_10000fdx_cap;
733 break;
734
735 case ETHER_STAT_LP_CAP_5000FDX:
736 *val = ixgbe->param_lp_5000fdx_cap;
737 break;
738
739 case ETHER_STAT_LP_CAP_2500FDX:
740 *val = ixgbe->param_lp_2500fdx_cap;
741 break;
742
743 case ETHER_STAT_LP_CAP_1000FDX:
744 *val = ixgbe->param_lp_1000fdx_cap;
745 break;
746
747 case ETHER_STAT_LP_CAP_100FDX:
748 *val = ixgbe->param_lp_100fdx_cap;
749 break;
750
751 case ETHER_STAT_LP_CAP_ASMPAUSE:
752 *val = ixgbe->param_lp_asym_pause_cap;
753 break;
754
755 case ETHER_STAT_LP_CAP_PAUSE:
756 *val = ixgbe->param_lp_pause_cap;
757 break;
758
759 case ETHER_STAT_LP_CAP_AUTONEG:
760 *val = ixgbe->param_lp_autoneg_cap;
761 break;
762
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