11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29 /*
30 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
31 */
32
33 #ifndef _IXGBE_OSDEP_H
34 #define _IXGBE_OSDEP_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include <sys/types.h>
41 #include <sys/byteorder.h>
42 #include <sys/conf.h>
43 #include <sys/debug.h>
44 #include <sys/stropts.h>
45 #include <sys/stream.h>
46 #include <sys/strlog.h>
47 #include <sys/kmem.h>
48 #include <sys/stat.h>
49 #include <sys/kstat.h>
50 #include <sys/modctl.h>
64 struct ixgbe_hw;
65 uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
66 void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t);
67
68 #define usec_delay(x) drv_usecwait(x)
69 #define msec_delay(x) drv_usecwait(x * 1000)
70
71 #define OS_DEP(hw) ((struct ixgbe_osdep *)((hw)->back))
72
73 #define false B_FALSE
74 #define true B_TRUE
75 #define FALSE B_FALSE
76 #define TRUE B_TRUE
77
78 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
79 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
80 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
81 #define PCI_COMMAND_REGISTER 0x04
82 #define PCI_EX_CONF_CAP 0xE0
83 #define SPEED_10GB 10000
84 #define SPEED_1GB 1000
85 #define SPEED_100 100
86 #define FULL_DUPLEX 2
87
88 #define IXGBE_WRITE_FLUSH(a) (void) IXGBE_READ_REG(a, IXGBE_STATUS)
89
90 #define IXGBE_WRITE_REG(a, reg, value) \
91 ddi_put32((OS_DEP(a))->reg_handle, \
92 (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value))
93
94 #define IXGBE_WRITE_REG_ARRAY(a, reg, index, value) \
95 IXGBE_WRITE_REG(a, ((reg) + ((index) << 2)), (value))
96
97 #define IXGBE_READ_REG(a, reg) \
98 ddi_get32((OS_DEP(a))->reg_handle, \
99 (uint32_t *)((uintptr_t)(a)->hw_addr + reg))
100
101 #define IXGBE_READ_REG_ARRAY(a, reg, index) \
102 IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
103
104 #define msec_delay_irq msec_delay
105 #define IXGBE_HTONL htonl
106 #define IXGBE_NTOHL ntohl
107 #define IXGBE_NTOHS ntohs
108
109 #ifdef _BIG_ENDIAN
110 #define IXGBE_CPU_TO_LE32 BSWAP_32
111 #define IXGBE_LE32_TO_CPUS BSWAP_32
112 #else
113 #define IXGBE_CPU_TO_LE32(x) (x)
114 #define IXGBE_LE32_TO_CPUS(x) (x)
115 #endif /* _BIG_ENDIAN */
116
117 #define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
118 #define UNREFERENCED_1PARAMETER(_p) UNREFERENCED_PARAMETER(_p)
119 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q))
120 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r))
121 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q,_r, _s))
122
123
124
125 typedef int8_t s8;
126 typedef int16_t s16;
127 typedef int32_t s32;
128 typedef int64_t s64;
129 typedef uint8_t u8;
130 typedef uint16_t u16;
131 typedef uint32_t u32;
132 typedef uint64_t u64;
133 typedef boolean_t bool;
134
135 struct ixgbe_osdep {
136 ddi_acc_handle_t reg_handle;
137 ddi_acc_handle_t cfg_handle;
138 struct ixgbe *ixgbe;
139 };
140
141 #ifdef __cplusplus
142 }
143 #endif
144
145 #endif /* _IXGBE_OSDEP_H */
|
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29 /*
30 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
31 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
32 */
33
34 #ifndef _IXGBE_OSDEP_H
35 #define _IXGBE_OSDEP_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #include <sys/types.h>
42 #include <sys/byteorder.h>
43 #include <sys/conf.h>
44 #include <sys/debug.h>
45 #include <sys/stropts.h>
46 #include <sys/stream.h>
47 #include <sys/strlog.h>
48 #include <sys/kmem.h>
49 #include <sys/stat.h>
50 #include <sys/kstat.h>
51 #include <sys/modctl.h>
65 struct ixgbe_hw;
66 uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
67 void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t);
68
69 #define usec_delay(x) drv_usecwait(x)
70 #define msec_delay(x) drv_usecwait(x * 1000)
71
72 #define OS_DEP(hw) ((struct ixgbe_osdep *)((hw)->back))
73
74 #define false B_FALSE
75 #define true B_TRUE
76 #define FALSE B_FALSE
77 #define TRUE B_TRUE
78
79 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
80 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
81 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
82 #define PCI_COMMAND_REGISTER 0x04
83 #define PCI_EX_CONF_CAP 0xE0
84 #define SPEED_10GB 10000
85 #define SPEED_5GB 5000
86 #define SPEED_2_5GB 2500
87 #define SPEED_1GB 1000
88 #define SPEED_100 100
89 #define FULL_DUPLEX 2
90
91 #define IXGBE_WRITE_FLUSH(a) (void) IXGBE_READ_REG(a, IXGBE_STATUS)
92
93 #define IXGBE_WRITE_REG(a, reg, value) \
94 ddi_put32((OS_DEP(a))->reg_handle, \
95 (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value))
96
97 #define IXGBE_WRITE_REG_ARRAY(a, reg, index, value) \
98 IXGBE_WRITE_REG(a, ((reg) + ((index) << 2)), (value))
99
100 #define IXGBE_READ_REG(a, reg) \
101 ddi_get32((OS_DEP(a))->reg_handle, \
102 (uint32_t *)((uintptr_t)(a)->hw_addr + reg))
103
104 #define IXGBE_READ_REG_ARRAY(a, reg, index) \
105 IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
106
107 #define msec_delay_irq msec_delay
108 #define IXGBE_HTONL htonl
109 #define IXGBE_NTOHL ntohl
110 #define IXGBE_NTOHS ntohs
111
112 #ifdef _BIG_ENDIAN
113 #define IXGBE_CPU_TO_LE32 BSWAP_32
114 #define IXGBE_LE32_TO_CPUS BSWAP_32
115 #define IXGBE_CPU_TO_BE16 (x)
116 #define IXGBE_CPU_TO_BE32 (x)
117 #else
118 #define IXGBE_CPU_TO_LE32(x) (x)
119 #define IXGBE_LE32_TO_CPUS(x) (x)
120 #define IXGBE_CPU_TO_BE16 BSWAP_16
121 #define IXGBE_CPU_TO_BE32 BSWAP_32
122 #endif /* _BIG_ENDIAN */
123
124 #define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
125 #define UNREFERENCED_1PARAMETER(_p) UNREFERENCED_PARAMETER(_p)
126 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q))
127 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r))
128 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q,_r, _s))
129
130
131
132 typedef int8_t s8;
133 typedef int16_t s16;
134 typedef int32_t s32;
135 typedef int64_t s64;
136 typedef uint8_t u8;
137 typedef uint16_t u16;
138 typedef uint32_t u32;
139 typedef uint64_t u64;
140 typedef boolean_t bool;
141
142 /* shared code requires this */
143 #define __le16 u16
144 #define __le32 u32
145 #define __le64 u64
146 #define __be16 u16
147 #define __be32 u32
148 #define __be64 u64
149
150 struct ixgbe_osdep {
151 ddi_acc_handle_t reg_handle;
152 ddi_acc_handle_t cfg_handle;
153 struct ixgbe *ixgbe;
154 };
155
156 #ifdef __cplusplus
157 }
158 #endif
159
160 #endif /* _IXGBE_OSDEP_H */
|