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6064 ixgbe needs X550 support
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--- old/usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c
+++ new/usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
33 +/*$FreeBSD$*/
34 34
35 35 #include "ixgbe_x540.h"
36 36 #include "ixgbe_type.h"
37 37 #include "ixgbe_api.h"
38 38 #include "ixgbe_common.h"
39 39 #include "ixgbe_phy.h"
40 40
41 -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
41 +#define IXGBE_X540_MAX_TX_QUEUES 128
42 +#define IXGBE_X540_MAX_RX_QUEUES 128
43 +#define IXGBE_X540_RAR_ENTRIES 128
44 +#define IXGBE_X540_MC_TBL_SIZE 128
45 +#define IXGBE_X540_VFT_TBL_SIZE 128
46 +#define IXGBE_X540_RX_PB_SIZE 384
47 +
42 48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
43 49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
44 50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
45 51
46 52 /**
47 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
48 54 * @hw: pointer to hardware structure
49 55 *
50 56 * Initialize the function pointers and assign the MAC type for X540.
51 57 * Does not touch the hardware.
52 58 **/
53 59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
54 60 {
55 61 struct ixgbe_mac_info *mac = &hw->mac;
56 62 struct ixgbe_phy_info *phy = &hw->phy;
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57 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 64 s32 ret_val;
59 65
60 66 DEBUGFUNC("ixgbe_init_ops_X540");
61 67
62 68 ret_val = ixgbe_init_phy_ops_generic(hw);
63 69 ret_val = ixgbe_init_ops_generic(hw);
64 70
65 71
66 72 /* EEPROM */
67 - eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
68 - eeprom->ops.read = &ixgbe_read_eerd_X540;
69 - eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
70 - eeprom->ops.write = &ixgbe_write_eewr_X540;
71 - eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
72 - eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
73 - eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
74 - eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
73 + eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
74 + eeprom->ops.read = ixgbe_read_eerd_X540;
75 + eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
76 + eeprom->ops.write = ixgbe_write_eewr_X540;
77 + eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
78 + eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
79 + eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
80 + eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
75 81
76 82 /* PHY */
77 - phy->ops.init = &ixgbe_init_phy_ops_generic;
83 + phy->ops.init = ixgbe_init_phy_ops_generic;
78 84 phy->ops.reset = NULL;
85 + phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
79 86
80 87 /* MAC */
81 - mac->ops.reset_hw = &ixgbe_reset_hw_X540;
82 - mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
83 - mac->ops.get_media_type = &ixgbe_get_media_type_X540;
88 + mac->ops.reset_hw = ixgbe_reset_hw_X540;
89 + mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
90 + mac->ops.get_media_type = ixgbe_get_media_type_X540;
84 91 mac->ops.get_supported_physical_layer =
85 - &ixgbe_get_supported_physical_layer_X540;
92 + ixgbe_get_supported_physical_layer_X540;
86 93 mac->ops.read_analog_reg8 = NULL;
87 94 mac->ops.write_analog_reg8 = NULL;
88 - mac->ops.start_hw = &ixgbe_start_hw_X540;
89 - mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
90 - mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
91 - mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
92 - mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
93 - mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
94 - mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
95 - mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
96 - mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
97 - mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
95 + mac->ops.start_hw = ixgbe_start_hw_X540;
96 + mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
97 + mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
98 + mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
99 + mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
100 + mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
101 + mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
102 + mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
103 + mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
104 + mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
98 105
99 106 /* RAR, Multicast, VLAN */
100 - mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
101 - mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
102 - mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
103 - mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
107 + mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
108 + mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
109 + mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
110 + mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
104 111 mac->rar_highwater = 1;
105 - mac->ops.set_vfta = &ixgbe_set_vfta_generic;
106 - mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
107 - mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
108 - mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
109 - mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
110 - mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
112 + mac->ops.set_vfta = ixgbe_set_vfta_generic;
113 + mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
114 + mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
115 + mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
116 + mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
117 + mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
111 118
112 119 /* Link */
113 120 mac->ops.get_link_capabilities =
114 - &ixgbe_get_copper_link_capabilities_generic;
115 - mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
116 - mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
117 - mac->ops.check_link = &ixgbe_check_mac_link_generic;
121 + ixgbe_get_copper_link_capabilities_generic;
122 + mac->ops.setup_link = ixgbe_setup_mac_link_X540;
123 + mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
124 + mac->ops.check_link = ixgbe_check_mac_link_generic;
118 125
119 - mac->mcft_size = 128;
120 - mac->vft_size = 128;
121 - mac->num_rar_entries = 128;
122 - mac->rx_pb_size = 384;
123 - mac->max_tx_queues = 128;
124 - mac->max_rx_queues = 128;
126 +
127 + mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
128 + mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
129 + mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
130 + mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
131 + mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
132 + mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
125 133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
126 134
127 135 /*
128 136 * FWSM register
129 137 * ARC supported; valid only if manageability features are
130 138 * enabled.
131 139 */
132 - mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
133 - IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
140 + mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
141 + & IXGBE_FWSM_MODE_MASK);
134 142
135 143 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
136 144
137 145 /* LEDs */
138 146 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 147 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140 148
141 149 /* Manageability interface */
142 - mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
150 + mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
143 151
152 + mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
153 +
144 154 return ret_val;
145 155 }
146 156
147 157 /**
148 158 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 159 * @hw: pointer to hardware structure
150 160 * @speed: pointer to link speed
151 161 * @autoneg: TRUE when autoneg or autotry is enabled
152 162 *
153 163 * Determines the link capabilities by reading the AUTOC register.
154 164 **/
155 165 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 166 ixgbe_link_speed *speed,
157 167 bool *autoneg)
158 168 {
159 - return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
169 + ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 +
171 + return IXGBE_SUCCESS;
160 172 }
161 173
162 174 /**
163 175 * ixgbe_get_media_type_X540 - Get media type
164 176 * @hw: pointer to hardware structure
165 177 *
166 178 * Returns the media type (fiber, copper, backplane)
167 179 **/
168 180 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
169 181 {
170 182 UNREFERENCED_1PARAMETER(hw);
171 183 return ixgbe_media_type_copper;
172 184 }
173 185
174 186 /**
175 187 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
176 188 * @hw: pointer to hardware structure
177 189 * @speed: new link speed
178 - * @autoneg: TRUE if autonegotiation enabled
179 190 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
180 191 **/
181 192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
182 - ixgbe_link_speed speed, bool autoneg,
193 + ixgbe_link_speed speed,
183 194 bool autoneg_wait_to_complete)
184 195 {
185 196 DEBUGFUNC("ixgbe_setup_mac_link_X540");
186 - return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
187 - autoneg_wait_to_complete);
197 + return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
188 198 }
189 199
190 200 /**
191 201 * ixgbe_reset_hw_X540 - Perform hardware reset
192 202 * @hw: pointer to hardware structure
193 203 *
194 204 * Resets the hardware by resetting the transmit and receive units, masks
195 205 * and clears all interrupts, and perform a reset.
196 206 **/
197 207 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
198 208 {
199 209 s32 status;
200 210 u32 ctrl, i;
201 211
202 212 DEBUGFUNC("ixgbe_reset_hw_X540");
203 213
204 214 /* Call adapter stop to disable tx/rx and clear interrupts */
205 215 status = hw->mac.ops.stop_adapter(hw);
206 216 if (status != IXGBE_SUCCESS)
207 217 goto reset_hw_out;
208 218
209 219 /* flush pending Tx transactions */
210 220 ixgbe_clear_tx_pending(hw);
211 221
212 222 mac_reset_top:
213 223 ctrl = IXGBE_CTRL_RST;
214 224 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
215 225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
216 226 IXGBE_WRITE_FLUSH(hw);
217 227
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218 228 /* Poll for reset bit to self-clear indicating reset is complete */
219 229 for (i = 0; i < 10; i++) {
220 230 usec_delay(1);
221 231 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
222 232 if (!(ctrl & IXGBE_CTRL_RST_MASK))
223 233 break;
224 234 }
225 235
226 236 if (ctrl & IXGBE_CTRL_RST_MASK) {
227 237 status = IXGBE_ERR_RESET_FAILED;
228 - DEBUGOUT("Reset polling failed to complete.\n");
238 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
239 + "Reset polling failed to complete.\n");
229 240 }
230 241 msec_delay(100);
231 242
232 243 /*
233 244 * Double resets are required for recovery from certain error
234 245 * conditions. Between resets, it is necessary to stall to allow time
235 246 * for any pending HW events to complete.
236 247 */
237 248 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
238 249 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
239 250 goto mac_reset_top;
240 251 }
241 252
242 253 /* Set the Rx packet buffer size. */
243 254 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
244 255
245 256 /* Store the permanent mac address */
246 257 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
247 258
248 259 /*
249 260 * Store MAC address from RAR0, clear receive address registers, and
250 261 * clear the multicast table. Also reset num_rar_entries to 128,
251 262 * since we modify this value when programming the SAN MAC address.
252 263 */
253 264 hw->mac.num_rar_entries = 128;
254 265 hw->mac.ops.init_rx_addrs(hw);
255 266
256 267 /* Store the permanent SAN mac address */
257 268 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
258 269
259 270 /* Add the SAN MAC address to the RAR only if it's a valid address */
260 271 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
261 272 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
262 273 hw->mac.san_addr, 0, IXGBE_RAH_AV);
263 274
264 275 /* Save the SAN MAC RAR index */
265 276 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
266 277
267 278 /* Reserve the last RAR for the SAN MAC address */
268 279 hw->mac.num_rar_entries--;
269 280 }
270 281
271 282 /* Store the alternative WWNN/WWPN prefix */
272 283 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
273 284 &hw->mac.wwpn_prefix);
274 285
275 286 reset_hw_out:
276 287 return status;
277 288 }
278 289
279 290 /**
280 291 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
281 292 * @hw: pointer to hardware structure
282 293 *
283 294 * Starts the hardware using the generic start_hw function
284 295 * and the generation start_hw function.
285 296 * Then performs revision-specific operations, if any.
286 297 **/
287 298 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
288 299 {
289 300 s32 ret_val = IXGBE_SUCCESS;
290 301
291 302 DEBUGFUNC("ixgbe_start_hw_X540");
292 303
293 304 ret_val = ixgbe_start_hw_generic(hw);
294 305 if (ret_val != IXGBE_SUCCESS)
295 306 goto out;
296 307
297 308 ret_val = ixgbe_start_hw_gen2(hw);
298 309
299 310 out:
300 311 return ret_val;
301 312 }
302 313
303 314 /**
304 315 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
305 316 * @hw: pointer to hardware structure
306 317 *
307 318 * Determines physical layer capabilities of the current configuration.
308 319 **/
309 320 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
310 321 {
311 322 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
312 323 u16 ext_ability = 0;
313 324
314 325 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
315 326
316 327 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
317 328 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
318 329 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
319 330 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
320 331 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
321 332 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
322 333 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
323 334 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
324 335
325 336 return physical_layer;
326 337 }
327 338
328 339 /**
329 340 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
330 341 * @hw: pointer to hardware structure
331 342 *
332 343 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
333 344 * ixgbe_hw struct in order to set up EEPROM access.
334 345 **/
335 346 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
336 347 {
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337 348 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
338 349 u32 eec;
339 350 u16 eeprom_size;
340 351
341 352 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
342 353
343 354 if (eeprom->type == ixgbe_eeprom_uninitialized) {
344 355 eeprom->semaphore_delay = 10;
345 356 eeprom->type = ixgbe_flash;
346 357
347 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
358 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
348 359 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
349 360 IXGBE_EEC_SIZE_SHIFT);
350 361 eeprom->word_size = 1 << (eeprom_size +
351 362 IXGBE_EEPROM_WORD_SIZE_SHIFT);
352 363
353 364 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
354 365 eeprom->type, eeprom->word_size);
355 366 }
356 367
357 368 return IXGBE_SUCCESS;
358 369 }
359 370
360 371 /**
361 372 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
362 373 * @hw: pointer to hardware structure
363 374 * @offset: offset of word in the EEPROM to read
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364 375 * @data: word read from the EEPROM
365 376 *
366 377 * Reads a 16 bit word from the EEPROM using the EERD register.
367 378 **/
368 379 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
369 380 {
370 381 s32 status = IXGBE_SUCCESS;
371 382
372 383 DEBUGFUNC("ixgbe_read_eerd_X540");
373 384 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
374 - IXGBE_SUCCESS)
385 + IXGBE_SUCCESS) {
375 386 status = ixgbe_read_eerd_generic(hw, offset, data);
376 - else
387 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
388 + } else {
377 389 status = IXGBE_ERR_SWFW_SYNC;
390 + }
378 391
379 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
380 392 return status;
381 393 }
382 394
383 395 /**
384 396 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
385 397 * @hw: pointer to hardware structure
386 398 * @offset: offset of word in the EEPROM to read
387 399 * @words: number of words
388 400 * @data: word(s) read from the EEPROM
389 401 *
390 402 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
391 403 **/
392 404 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
393 405 u16 offset, u16 words, u16 *data)
394 406 {
395 407 s32 status = IXGBE_SUCCESS;
396 408
397 409 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
398 410 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
399 - IXGBE_SUCCESS)
411 + IXGBE_SUCCESS) {
400 412 status = ixgbe_read_eerd_buffer_generic(hw, offset,
401 413 words, data);
402 - else
414 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
415 + } else {
403 416 status = IXGBE_ERR_SWFW_SYNC;
417 + }
404 418
405 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
406 419 return status;
407 420 }
408 421
409 422 /**
410 423 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
411 424 * @hw: pointer to hardware structure
412 425 * @offset: offset of word in the EEPROM to write
413 426 * @data: word write to the EEPROM
414 427 *
415 428 * Write a 16 bit word to the EEPROM using the EEWR register.
416 429 **/
417 430 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
418 431 {
419 432 s32 status = IXGBE_SUCCESS;
420 433
421 434 DEBUGFUNC("ixgbe_write_eewr_X540");
422 435 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
423 - IXGBE_SUCCESS)
436 + IXGBE_SUCCESS) {
424 437 status = ixgbe_write_eewr_generic(hw, offset, data);
425 - else
438 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
439 + } else {
426 440 status = IXGBE_ERR_SWFW_SYNC;
441 + }
427 442
428 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
429 443 return status;
430 444 }
431 445
432 446 /**
433 447 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
434 448 * @hw: pointer to hardware structure
435 449 * @offset: offset of word in the EEPROM to write
436 450 * @words: number of words
437 451 * @data: word(s) write to the EEPROM
438 452 *
439 453 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
440 454 **/
441 455 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
442 456 u16 offset, u16 words, u16 *data)
443 457 {
444 458 s32 status = IXGBE_SUCCESS;
445 459
446 460 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
447 461 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
448 - IXGBE_SUCCESS)
462 + IXGBE_SUCCESS) {
449 463 status = ixgbe_write_eewr_buffer_generic(hw, offset,
450 464 words, data);
451 - else
465 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
466 + } else {
452 467 status = IXGBE_ERR_SWFW_SYNC;
468 + }
453 469
454 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
455 470 return status;
456 471 }
457 472
458 473 /**
459 474 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
460 475 *
461 476 * This function does not use synchronization for EERD and EEWR. It can
462 477 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
463 478 *
464 479 * @hw: pointer to hardware structure
480 + *
481 + * Returns a negative error code on error, or the 16-bit checksum
465 482 **/
466 -u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
483 +s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
467 484 {
468 - u16 i;
469 - u16 j;
485 + u16 i, j;
470 486 u16 checksum = 0;
471 487 u16 length = 0;
472 488 u16 pointer = 0;
473 489 u16 word = 0;
490 + u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
491 + u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
474 492
475 - /*
476 - * Do not use hw->eeprom.ops.read because we do not want to take
493 + /* Do not use hw->eeprom.ops.read because we do not want to take
477 494 * the synchronization semaphores here. Instead use
478 495 * ixgbe_read_eerd_generic
479 496 */
480 497
481 498 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
482 499
483 500 /* Include 0x0-0x3F in the checksum */
484 - for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
485 - if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
501 + for (i = 0; i <= checksum_last_word; i++) {
502 + if (ixgbe_read_eerd_generic(hw, i, &word)) {
486 503 DEBUGOUT("EEPROM read failed\n");
487 - break;
504 + return IXGBE_ERR_EEPROM;
488 505 }
489 - checksum += word;
506 + if (i != IXGBE_EEPROM_CHECKSUM)
507 + checksum += word;
490 508 }
491 509
492 - /*
493 - * Include all data from pointers 0x3, 0x6-0xE. This excludes the
510 + /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
494 511 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
495 512 */
496 - for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
513 + for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
497 514 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
498 515 continue;
499 516
500 - if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
517 + if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
501 518 DEBUGOUT("EEPROM read failed\n");
502 - break;
519 + return IXGBE_ERR_EEPROM;
503 520 }
504 521
505 522 /* Skip pointer section if the pointer is invalid. */
506 523 if (pointer == 0xFFFF || pointer == 0 ||
507 524 pointer >= hw->eeprom.word_size)
508 525 continue;
509 526
510 - if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
511 - IXGBE_SUCCESS) {
527 + if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
512 528 DEBUGOUT("EEPROM read failed\n");
513 - break;
529 + return IXGBE_ERR_EEPROM;
514 530 }
515 531
516 532 /* Skip pointer section if length is invalid. */
517 533 if (length == 0xFFFF || length == 0 ||
518 534 (pointer + length) >= hw->eeprom.word_size)
519 535 continue;
520 536
521 - for (j = pointer+1; j <= pointer+length; j++) {
522 - if (ixgbe_read_eerd_generic(hw, j, &word) !=
523 - IXGBE_SUCCESS) {
537 + for (j = pointer + 1; j <= pointer + length; j++) {
538 + if (ixgbe_read_eerd_generic(hw, j, &word)) {
524 539 DEBUGOUT("EEPROM read failed\n");
525 - break;
540 + return IXGBE_ERR_EEPROM;
526 541 }
527 542 checksum += word;
528 543 }
529 544 }
530 545
531 546 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
532 547
533 - return checksum;
548 + return (s32)checksum;
534 549 }
535 550
536 551 /**
537 552 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
538 553 * @hw: pointer to hardware structure
539 554 * @checksum_val: calculated checksum
540 555 *
541 556 * Performs checksum calculation and validates the EEPROM checksum. If the
542 557 * caller does not need checksum_val, the value can be NULL.
543 558 **/
544 559 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
545 560 u16 *checksum_val)
546 561 {
547 562 s32 status;
548 563 u16 checksum;
549 564 u16 read_checksum = 0;
550 565
551 566 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
552 567
553 - /*
554 - * Read the first word from the EEPROM. If this times out or fails, do
568 + /* Read the first word from the EEPROM. If this times out or fails, do
555 569 * not continue or we could be in for a very long wait while every
556 570 * EEPROM read fails
557 571 */
558 572 status = hw->eeprom.ops.read(hw, 0, &checksum);
559 -
560 - if (status != IXGBE_SUCCESS) {
573 + if (status) {
561 574 DEBUGOUT("EEPROM read failed\n");
562 - goto out;
575 + return status;
563 576 }
564 577
565 - if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
566 - IXGBE_SUCCESS) {
567 - checksum = hw->eeprom.ops.calc_checksum(hw);
578 + if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
579 + return IXGBE_ERR_SWFW_SYNC;
568 580
569 - /*
570 - * Do not use hw->eeprom.ops.read because we do not want to take
571 - * the synchronization semaphores twice here.
572 - */
573 - status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
574 - &read_checksum);
581 + status = hw->eeprom.ops.calc_checksum(hw);
582 + if (status < 0)
583 + goto out;
575 584
576 - if (status == IXGBE_SUCCESS) {
577 - /*
578 - * Verify read checksum from EEPROM is the same as
579 - * calculated checksum
580 - */
581 - if (read_checksum != checksum)
582 - status = IXGBE_ERR_EEPROM_CHECKSUM;
585 + checksum = (u16)(status & 0xffff);
583 586
584 - /* If the user cares, return the calculated checksum */
585 - if (checksum_val)
586 - *checksum_val = checksum;
587 - }
588 - } else {
589 - status = IXGBE_ERR_SWFW_SYNC;
587 + /* Do not use hw->eeprom.ops.read because we do not want to take
588 + * the synchronization semaphores twice here.
589 + */
590 + status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
591 + &read_checksum);
592 + if (status)
593 + goto out;
594 +
595 + /* Verify read checksum from EEPROM is the same as
596 + * calculated checksum
597 + */
598 + if (read_checksum != checksum) {
599 + ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
600 + "Invalid EEPROM checksum");
601 + status = IXGBE_ERR_EEPROM_CHECKSUM;
590 602 }
591 603
592 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
604 + /* If the user cares, return the calculated checksum */
605 + if (checksum_val)
606 + *checksum_val = checksum;
607 +
593 608 out:
609 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
610 +
594 611 return status;
595 612 }
596 613
597 614 /**
598 615 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 616 * @hw: pointer to hardware structure
600 617 *
601 618 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 619 * checksum and updates the EEPROM and instructs the hardware to update
603 620 * the flash.
604 621 **/
605 622 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 623 {
607 624 s32 status;
608 625 u16 checksum;
609 626
610 627 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
611 628
612 - /*
613 - * Read the first word from the EEPROM. If this times out or fails, do
629 + /* Read the first word from the EEPROM. If this times out or fails, do
614 630 * not continue or we could be in for a very long wait while every
615 631 * EEPROM read fails
616 632 */
617 633 status = hw->eeprom.ops.read(hw, 0, &checksum);
618 -
619 - if (status != IXGBE_SUCCESS)
634 + if (status) {
620 635 DEBUGOUT("EEPROM read failed\n");
636 + return status;
637 + }
621 638
622 - if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
623 - IXGBE_SUCCESS) {
624 - checksum = hw->eeprom.ops.calc_checksum(hw);
639 + if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
640 + return IXGBE_ERR_SWFW_SYNC;
625 641
626 - /*
627 - * Do not use hw->eeprom.ops.write because we do not want to
628 - * take the synchronization semaphores twice here.
629 - */
630 - status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
631 - checksum);
642 + status = hw->eeprom.ops.calc_checksum(hw);
643 + if (status < 0)
644 + goto out;
632 645
633 - if (status == IXGBE_SUCCESS)
634 - status = ixgbe_update_flash_X540(hw);
635 - else
636 - status = IXGBE_ERR_SWFW_SYNC;
637 - }
646 + checksum = (u16)(status & 0xffff);
638 647
648 + /* Do not use hw->eeprom.ops.write because we do not want to
649 + * take the synchronization semaphores twice here.
650 + */
651 + status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
652 + if (status)
653 + goto out;
654 +
655 + status = ixgbe_update_flash_X540(hw);
656 +
657 +out:
639 658 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
640 659
641 660 return status;
642 661 }
643 662
644 663 /**
645 664 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
646 665 * @hw: pointer to hardware structure
647 666 *
648 667 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
649 668 * EEPROM from shadow RAM to the flash device.
650 669 **/
651 -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
670 +s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
652 671 {
653 672 u32 flup;
654 - s32 status = IXGBE_ERR_EEPROM;
673 + s32 status;
655 674
656 675 DEBUGFUNC("ixgbe_update_flash_X540");
657 676
658 677 status = ixgbe_poll_flash_update_done_X540(hw);
659 678 if (status == IXGBE_ERR_EEPROM) {
660 679 DEBUGOUT("Flash update time out\n");
661 680 goto out;
662 681 }
663 682
664 - flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
665 - IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
683 + flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
684 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
666 685
667 686 status = ixgbe_poll_flash_update_done_X540(hw);
668 687 if (status == IXGBE_SUCCESS)
669 688 DEBUGOUT("Flash update complete\n");
670 689 else
671 690 DEBUGOUT("Flash update time out\n");
672 691
673 - if (hw->revision_id == 0) {
674 - flup = IXGBE_READ_REG(hw, IXGBE_EEC);
692 + if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
693 + flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
675 694
676 695 if (flup & IXGBE_EEC_SEC1VAL) {
677 696 flup |= IXGBE_EEC_FLUP;
678 - IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
697 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
679 698 }
680 699
681 700 status = ixgbe_poll_flash_update_done_X540(hw);
682 701 if (status == IXGBE_SUCCESS)
683 702 DEBUGOUT("Flash update complete\n");
684 703 else
685 704 DEBUGOUT("Flash update time out\n");
686 705 }
687 706 out:
688 707 return status;
689 708 }
690 709
691 710 /**
692 711 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
693 712 * @hw: pointer to hardware structure
694 713 *
695 714 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
696 715 * flash update is done.
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697 716 **/
698 717 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
699 718 {
700 719 u32 i;
701 720 u32 reg;
702 721 s32 status = IXGBE_ERR_EEPROM;
703 722
704 723 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
705 724
706 725 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
707 - reg = IXGBE_READ_REG(hw, IXGBE_EEC);
726 + reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
708 727 if (reg & IXGBE_EEC_FLUDONE) {
709 728 status = IXGBE_SUCCESS;
710 729 break;
711 730 }
712 - usec_delay(5);
731 + msec_delay(5);
713 732 }
733 +
734 + if (i == IXGBE_FLUDONE_ATTEMPTS)
735 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
736 + "Flash update status polling timed out");
737 +
714 738 return status;
715 739 }
716 740
717 741 /**
718 742 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
719 743 * @hw: pointer to hardware structure
720 744 * @mask: Mask to specify which semaphore to acquire
721 745 *
722 746 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
723 747 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
724 748 **/
725 -s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
749 +s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
726 750 {
727 - u32 swfw_sync;
728 - u32 swmask = mask;
729 - u32 fwmask = mask << 5;
730 - u32 hwmask = 0;
751 + u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
752 + u32 fwmask = swmask << 5;
753 + u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
731 754 u32 timeout = 200;
755 + u32 hwmask = 0;
756 + u32 swfw_sync;
732 757 u32 i;
733 - s32 ret_val = IXGBE_SUCCESS;
734 758
735 759 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
736 760
737 - if (swmask == IXGBE_GSSR_EEP_SM)
738 - hwmask = IXGBE_GSSR_FLASH_SM;
761 + if (swmask & IXGBE_GSSR_EEP_SM)
762 + hwmask |= IXGBE_GSSR_FLASH_SM;
739 763
740 764 /* SW only mask doesn't have FW bit pair */
741 - if (swmask == IXGBE_GSSR_SW_MNG_SM)
742 - fwmask = 0;
765 + if (mask & IXGBE_GSSR_SW_MNG_SM)
766 + swmask |= IXGBE_GSSR_SW_MNG_SM;
743 767
768 + swmask |= swi2c_mask;
769 + fwmask |= swi2c_mask << 2;
744 770 for (i = 0; i < timeout; i++) {
745 - /*
746 - * SW NVM semaphore bit is used for access to all
771 + /* SW NVM semaphore bit is used for access to all
747 772 * SW_FW_SYNC bits (not just NVM)
748 773 */
749 - if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 - ret_val = IXGBE_ERR_SWFW_SYNC;
751 - goto out;
752 - }
774 + if (ixgbe_get_swfw_sync_semaphore(hw))
775 + return IXGBE_ERR_SWFW_SYNC;
753 776
754 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
777 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
755 778 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
756 779 swfw_sync |= swmask;
757 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
780 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
781 + swfw_sync);
758 782 ixgbe_release_swfw_sync_semaphore(hw);
759 783 msec_delay(5);
760 - goto out;
761 - } else {
762 - /*
763 - * Firmware currently using resource (fwmask), hardware
764 - * currently using resource (hwmask), or other software
765 - * thread currently using resource (swmask)
766 - */
767 - ixgbe_release_swfw_sync_semaphore(hw);
768 - msec_delay(5);
784 + return IXGBE_SUCCESS;
769 785 }
786 + /* Firmware currently using resource (fwmask), hardware
787 + * currently using resource (hwmask), or other software
788 + * thread currently using resource (swmask)
789 + */
790 + ixgbe_release_swfw_sync_semaphore(hw);
791 + msec_delay(5);
770 792 }
771 793
772 794 /* Failed to get SW only semaphore */
773 795 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
774 - ret_val = IXGBE_ERR_SWFW_SYNC;
775 - goto out;
796 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
797 + "Failed to get SW only semaphore");
798 + return IXGBE_ERR_SWFW_SYNC;
776 799 }
777 800
778 801 /* If the resource is not released by the FW/HW the SW can assume that
779 - * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
802 + * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
780 803 * of the requested resource(s) while ignoring the corresponding FW/HW
781 804 * bits in the SW_FW_SYNC register.
782 805 */
783 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
806 + if (ixgbe_get_swfw_sync_semaphore(hw))
807 + return IXGBE_ERR_SWFW_SYNC;
808 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
784 809 if (swfw_sync & (fwmask | hwmask)) {
785 - if (ixgbe_get_swfw_sync_semaphore(hw)) {
786 - ret_val = IXGBE_ERR_SWFW_SYNC;
787 - goto out;
788 - }
789 -
790 810 swfw_sync |= swmask;
791 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
811 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
792 812 ixgbe_release_swfw_sync_semaphore(hw);
793 813 msec_delay(5);
814 + return IXGBE_SUCCESS;
794 815 }
816 + /* If the resource is not released by other SW the SW can assume that
817 + * the other SW malfunctions. In that case the SW should clear all SW
818 + * flags that it does not own and then repeat the whole process once
819 + * again.
820 + */
821 + if (swfw_sync & swmask) {
822 + u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
823 + IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
795 824
796 -out:
797 - return ret_val;
825 + if (swi2c_mask)
826 + rmask |= IXGBE_GSSR_I2C_MASK;
827 + ixgbe_release_swfw_sync_X540(hw, rmask);
828 + ixgbe_release_swfw_sync_semaphore(hw);
829 + return IXGBE_ERR_SWFW_SYNC;
830 + }
831 + ixgbe_release_swfw_sync_semaphore(hw);
832 +
833 + return IXGBE_ERR_SWFW_SYNC;
798 834 }
799 835
800 836 /**
801 837 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 838 * @hw: pointer to hardware structure
803 839 * @mask: Mask to specify which semaphore to release
804 840 *
805 841 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 842 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 843 **/
808 -void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
844 +void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
809 845 {
846 + u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
810 847 u32 swfw_sync;
811 - u32 swmask = mask;
812 848
813 849 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814 850
815 - (void) ixgbe_get_swfw_sync_semaphore(hw);
851 + if (mask & IXGBE_GSSR_I2C_MASK)
852 + swmask |= mask & IXGBE_GSSR_I2C_MASK;
853 + ixgbe_get_swfw_sync_semaphore(hw);
816 854
817 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
855 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
818 856 swfw_sync &= ~swmask;
819 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
857 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
820 858
821 859 ixgbe_release_swfw_sync_semaphore(hw);
822 860 msec_delay(5);
823 861 }
824 862
825 863 /**
826 - * ixgbe_get_nvm_semaphore - Get hardware semaphore
864 + * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
827 865 * @hw: pointer to hardware structure
828 866 *
829 867 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 868 **/
831 869 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 870 {
833 871 s32 status = IXGBE_ERR_EEPROM;
834 872 u32 timeout = 2000;
835 873 u32 i;
836 874 u32 swsm;
837 875
838 876 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
839 877
840 878 /* Get SMBI software semaphore between device drivers first */
841 879 for (i = 0; i < timeout; i++) {
842 880 /*
843 881 * If the SMBI bit is 0 when we read it, then the bit will be
844 882 * set and we have the semaphore
845 883 */
846 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
884 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
847 885 if (!(swsm & IXGBE_SWSM_SMBI)) {
848 886 status = IXGBE_SUCCESS;
849 887 break;
850 888 }
851 889 usec_delay(50);
852 890 }
853 891
854 892 /* Now get the semaphore between SW/FW through the REGSMP bit */
855 893 if (status == IXGBE_SUCCESS) {
856 894 for (i = 0; i < timeout; i++) {
857 - swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
895 + swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
858 896 if (!(swsm & IXGBE_SWFW_REGSMP))
859 897 break;
860 898
861 899 usec_delay(50);
862 900 }
863 901
864 902 /*
865 903 * Release semaphores and return error if SW NVM semaphore
866 904 * was not granted because we don't have access to the EEPROM
867 905 */
868 906 if (i >= timeout) {
869 - DEBUGOUT("REGSMP Software NVM semaphore not "
870 - "granted.\n");
907 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
908 + "REGSMP Software NVM semaphore not granted.\n");
871 909 ixgbe_release_swfw_sync_semaphore(hw);
872 910 status = IXGBE_ERR_EEPROM;
873 911 }
874 912 } else {
875 - DEBUGOUT("Software semaphore SMBI between device drivers "
876 - "not granted.\n");
913 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
914 + "Software semaphore SMBI between device drivers "
915 + "not granted.\n");
877 916 }
878 917
879 918 return status;
880 919 }
881 920
882 921 /**
883 - * ixgbe_release_nvm_semaphore - Release hardware semaphore
922 + * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
884 923 * @hw: pointer to hardware structure
885 924 *
886 925 * This function clears hardware semaphore bits.
887 926 **/
888 927 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
889 928 {
890 929 u32 swsm;
891 930
892 931 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
893 932
894 933 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
895 934
896 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
897 - swsm &= ~IXGBE_SWSM_SMBI;
898 - IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
899 -
900 - swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
935 + swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
901 936 swsm &= ~IXGBE_SWFW_REGSMP;
902 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
937 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
903 938
939 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
940 + swsm &= ~IXGBE_SWSM_SMBI;
941 + IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
942 +
904 943 IXGBE_WRITE_FLUSH(hw);
905 944 }
906 945
907 946 /**
908 947 * ixgbe_blink_led_start_X540 - Blink LED based on index.
909 948 * @hw: pointer to hardware structure
910 949 * @index: led number to blink
911 950 *
912 951 * Devices that implement the version 2 interface:
913 952 * X540
914 953 **/
915 954 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
916 955 {
917 956 u32 macc_reg;
918 957 u32 ledctl_reg;
919 958 ixgbe_link_speed speed;
920 959 bool link_up;
921 960
922 961 DEBUGFUNC("ixgbe_blink_led_start_X540");
923 962
924 963 /*
925 964 * Link should be up in order for the blink bit in the LED control
926 965 * register to work. Force link and speed in the MAC if link is down.
927 966 * This will be reversed when we stop the blinking.
928 967 */
929 968 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
930 969 if (link_up == FALSE) {
931 970 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
932 971 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
933 972 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
934 973 }
935 974 /* Set the LED to LINK_UP + BLINK. */
936 975 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
937 976 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
938 977 ledctl_reg |= IXGBE_LED_BLINK(index);
939 978 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
940 979 IXGBE_WRITE_FLUSH(hw);
941 980
942 981 return IXGBE_SUCCESS;
943 982 }
944 983
945 984 /**
946 985 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
947 986 * @hw: pointer to hardware structure
948 987 * @index: led number to stop blinking
949 988 *
950 989 * Devices that implement the version 2 interface:
951 990 * X540
952 991 **/
953 992 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
954 993 {
955 994 u32 macc_reg;
956 995 u32 ledctl_reg;
957 996
958 997 DEBUGFUNC("ixgbe_blink_led_stop_X540");
959 998
960 999 /* Restore the LED to its default value. */
961 1000 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
962 1001 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
963 1002 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
964 1003 ledctl_reg &= ~IXGBE_LED_BLINK(index);
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965 1004 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
966 1005
967 1006 /* Unforce link and speed in the MAC. */
968 1007 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
969 1008 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
970 1009 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
971 1010 IXGBE_WRITE_FLUSH(hw);
972 1011
973 1012 return IXGBE_SUCCESS;
974 1013 }
975 -
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