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6064 ixgbe needs X550 support
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--- old/usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
+++ new/usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
33 +/*$FreeBSD$*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37 #include "ixgbe_phy.h"
38 38
39 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 -static bool ixgbe_get_i2c_data(u32 *i2cctl);
49 +static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
50 +static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 + u8 *sff8472_data);
50 52
51 53 /**
54 + * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
55 + * @hw: pointer to the hardware structure
56 + * @byte: byte to send
57 + *
58 + * Returns an error code on error.
59 + */
60 +static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
61 +{
62 + s32 status;
63 +
64 + status = ixgbe_clock_out_i2c_byte(hw, byte);
65 + if (status)
66 + return status;
67 + return ixgbe_get_i2c_ack(hw);
68 +}
69 +
70 +/**
71 + * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
72 + * @hw: pointer to the hardware structure
73 + * @byte: pointer to a u8 to receive the byte
74 + *
75 + * Returns an error code on error.
76 + */
77 +static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
78 +{
79 + s32 status;
80 +
81 + status = ixgbe_clock_in_i2c_byte(hw, byte);
82 + if (status)
83 + return status;
84 + /* ACK */
85 + return ixgbe_clock_out_i2c_bit(hw, FALSE);
86 +}
87 +
88 +/**
89 + * ixgbe_ones_comp_byte_add - Perform one's complement addition
90 + * @add1 - addend 1
91 + * @add2 - addend 2
92 + *
93 + * Returns one's complement 8-bit sum.
94 + */
95 +static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 +{
97 + u16 sum = add1 + add2;
98 +
99 + sum = (sum & 0xFF) + (sum >> 8);
100 + return sum & 0xFF;
101 +}
102 +
103 +/**
104 + * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
105 + * @hw: pointer to the hardware structure
106 + * @addr: I2C bus address to read from
107 + * @reg: I2C device register to read from
108 + * @val: pointer to location to receive read value
109 + * @lock: TRUE if to take and release semaphore
110 + *
111 + * Returns an error code on error.
112 + */
113 +static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
114 + u16 reg, u16 *val, bool lock)
115 +{
116 + u32 swfw_mask = hw->phy.phy_semaphore_mask;
117 + int max_retry = 10;
118 + int retry = 0;
119 + u8 csum_byte;
120 + u8 high_bits;
121 + u8 low_bits;
122 + u8 reg_high;
123 + u8 csum;
124 +
125 + if (hw->mac.type >= ixgbe_mac_X550)
126 + max_retry = 3;
127 + reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
128 + csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
129 + csum = ~csum;
130 + do {
131 + if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
132 + return IXGBE_ERR_SWFW_SYNC;
133 + ixgbe_i2c_start(hw);
134 + /* Device Address and write indication */
135 + if (ixgbe_out_i2c_byte_ack(hw, addr))
136 + goto fail;
137 + /* Write bits 14:8 */
138 + if (ixgbe_out_i2c_byte_ack(hw, reg_high))
139 + goto fail;
140 + /* Write bits 7:0 */
141 + if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
142 + goto fail;
143 + /* Write csum */
144 + if (ixgbe_out_i2c_byte_ack(hw, csum))
145 + goto fail;
146 + /* Re-start condition */
147 + ixgbe_i2c_start(hw);
148 + /* Device Address and read indication */
149 + if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
150 + goto fail;
151 + /* Get upper bits */
152 + if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
153 + goto fail;
154 + /* Get low bits */
155 + if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
156 + goto fail;
157 + /* Get csum */
158 + if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
159 + goto fail;
160 + /* NACK */
161 + if (ixgbe_clock_out_i2c_bit(hw, FALSE))
162 + goto fail;
163 + ixgbe_i2c_stop(hw);
164 + if (lock)
165 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
166 + *val = (high_bits << 8) | low_bits;
167 + return 0;
168 +
169 +fail:
170 + ixgbe_i2c_bus_clear(hw);
171 + if (lock)
172 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 + retry++;
174 + if (retry < max_retry)
175 + DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 + else
177 + DEBUGOUT("I2C byte read combined error.\n");
178 + } while (retry < max_retry);
179 +
180 + return IXGBE_ERR_I2C;
181 +}
182 +
183 +/**
184 + * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
185 + * @hw: pointer to the hardware structure
186 + * @addr: I2C bus address to read from
187 + * @reg: I2C device register to read from
188 + * @val: pointer to location to receive read value
189 + *
190 + * Returns an error code on error.
191 + **/
192 +static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
193 + u16 reg, u16 *val)
194 +{
195 + return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
196 +}
197 +
198 +/**
199 + * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
200 + * @hw: pointer to the hardware structure
201 + * @addr: I2C bus address to read from
202 + * @reg: I2C device register to read from
203 + * @val: pointer to location to receive read value
204 + *
205 + * Returns an error code on error.
206 + **/
207 +static s32
208 +ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
209 + u16 reg, u16 *val)
210 +{
211 + return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
212 +}
213 +
214 +/**
215 + * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
216 + * @hw: pointer to the hardware structure
217 + * @addr: I2C bus address to write to
218 + * @reg: I2C device register to write to
219 + * @val: value to write
220 + * @lock: TRUE if to take and release semaphore
221 + *
222 + * Returns an error code on error.
223 + */
224 +static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
225 + u16 reg, u16 val, bool lock)
226 +{
227 + u32 swfw_mask = hw->phy.phy_semaphore_mask;
228 + int max_retry = 1;
229 + int retry = 0;
230 + u8 reg_high;
231 + u8 csum;
232 +
233 + reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
234 + csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
235 + csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
236 + csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
237 + csum = ~csum;
238 + do {
239 + if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
240 + return IXGBE_ERR_SWFW_SYNC;
241 + ixgbe_i2c_start(hw);
242 + /* Device Address and write indication */
243 + if (ixgbe_out_i2c_byte_ack(hw, addr))
244 + goto fail;
245 + /* Write bits 14:8 */
246 + if (ixgbe_out_i2c_byte_ack(hw, reg_high))
247 + goto fail;
248 + /* Write bits 7:0 */
249 + if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
250 + goto fail;
251 + /* Write data 15:8 */
252 + if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
253 + goto fail;
254 + /* Write data 7:0 */
255 + if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
256 + goto fail;
257 + /* Write csum */
258 + if (ixgbe_out_i2c_byte_ack(hw, csum))
259 + goto fail;
260 + ixgbe_i2c_stop(hw);
261 + if (lock)
262 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
263 + return 0;
264 +
265 +fail:
266 + ixgbe_i2c_bus_clear(hw);
267 + if (lock)
268 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
269 + retry++;
270 + if (retry < max_retry)
271 + DEBUGOUT("I2C byte write combined error - Retrying.\n");
272 + else
273 + DEBUGOUT("I2C byte write combined error.\n");
274 + } while (retry < max_retry);
275 +
276 + return IXGBE_ERR_I2C;
277 +}
278 +
279 +/**
280 + * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
281 + * @hw: pointer to the hardware structure
282 + * @addr: I2C bus address to write to
283 + * @reg: I2C device register to write to
284 + * @val: value to write
285 + *
286 + * Returns an error code on error.
287 + **/
288 +static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
289 + u8 addr, u16 reg, u16 val)
290 +{
291 + return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
292 +}
293 +
294 +/**
295 + * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
296 + * @hw: pointer to the hardware structure
297 + * @addr: I2C bus address to write to
298 + * @reg: I2C device register to write to
299 + * @val: value to write
300 + *
301 + * Returns an error code on error.
302 + **/
303 +static s32
304 +ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
305 + u8 addr, u16 reg, u16 val)
306 +{
307 + return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
308 +}
309 +
310 +/**
52 311 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 312 * @hw: pointer to the hardware structure
54 313 *
55 314 * Initialize the function pointers.
56 315 **/
57 316 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
58 317 {
59 318 struct ixgbe_phy_info *phy = &hw->phy;
60 319
61 320 DEBUGFUNC("ixgbe_init_phy_ops_generic");
62 321
63 322 /* PHY */
64 - phy->ops.identify = &ixgbe_identify_phy_generic;
65 - phy->ops.reset = &ixgbe_reset_phy_generic;
66 - phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 - phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 - phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 - phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
323 + phy->ops.identify = ixgbe_identify_phy_generic;
324 + phy->ops.reset = ixgbe_reset_phy_generic;
325 + phy->ops.read_reg = ixgbe_read_phy_reg_generic;
326 + phy->ops.write_reg = ixgbe_write_phy_reg_generic;
327 + phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
328 + phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
329 + phy->ops.setup_link = ixgbe_setup_phy_link_generic;
330 + phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
70 331 phy->ops.check_link = NULL;
71 332 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 - phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 - phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
74 - phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 - phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 - phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 - phy->ops.identify_sfp = &ixgbe_identify_module_generic;
333 + phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
334 + phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
335 + phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
336 + phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
337 + phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
338 + phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
339 + phy->ops.identify_sfp = ixgbe_identify_module_generic;
78 340 phy->sfp_type = ixgbe_sfp_type_unknown;
79 - phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
341 + phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
342 + phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
343 + phy->ops.read_i2c_combined_unlocked =
344 + ixgbe_read_i2c_combined_generic_unlocked;
345 + phy->ops.write_i2c_combined_unlocked =
346 + ixgbe_write_i2c_combined_generic_unlocked;
347 + phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
348 + phy->ops.write_i2c_byte_unlocked =
349 + ixgbe_write_i2c_byte_generic_unlocked;
350 + phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
80 351 return IXGBE_SUCCESS;
81 352 }
82 353
83 354 /**
84 355 * ixgbe_identify_phy_generic - Get physical layer module
85 356 * @hw: pointer to hardware structure
86 357 *
87 358 * Determines the physical layer module found on the current adapter.
88 359 **/
89 360 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 361 {
91 362 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 363 u32 phy_addr;
93 364 u16 ext_ability = 0;
94 365
95 366 DEBUGFUNC("ixgbe_identify_phy_generic");
96 367
368 + if (!hw->phy.phy_semaphore_mask) {
369 + if (hw->bus.lan_id)
370 + hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
371 + else
372 + hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
373 + }
374 +
97 375 if (hw->phy.type == ixgbe_phy_unknown) {
98 376 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 377 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 378 hw->phy.addr = phy_addr;
101 - (void) ixgbe_get_phy_id(hw);
379 + ixgbe_get_phy_id(hw);
102 380 hw->phy.type =
103 381 ixgbe_get_phy_type_from_id(hw->phy.id);
104 382
105 383 if (hw->phy.type == ixgbe_phy_unknown) {
106 384 hw->phy.ops.read_reg(hw,
107 385 IXGBE_MDIO_PHY_EXT_ABILITY,
108 386 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 387 &ext_ability);
110 388 if (ext_ability &
111 389 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 390 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 391 hw->phy.type =
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114 392 ixgbe_phy_cu_unknown;
115 393 else
116 394 hw->phy.type =
117 395 ixgbe_phy_generic;
118 396 }
119 397
120 398 status = IXGBE_SUCCESS;
121 399 break;
122 400 }
123 401 }
124 - /* clear value if nothing found */
125 - if (status != IXGBE_SUCCESS)
402 +
403 + /* Certain media types do not have a phy so an address will not
404 + * be found and the code will take this path. Caller has to
405 + * decide if it is an error or not.
406 + */
407 + if (status != IXGBE_SUCCESS) {
126 408 hw->phy.addr = 0;
409 + }
127 410 } else {
128 411 status = IXGBE_SUCCESS;
129 412 }
130 413
131 414 return status;
132 415 }
133 416
134 417 /**
418 + * ixgbe_check_reset_blocked - check status of MNG FW veto bit
419 + * @hw: pointer to the hardware structure
420 + *
421 + * This function checks the MMNGC.MNG_VETO bit to see if there are
422 + * any constraints on link from manageability. For MAC's that don't
423 + * have this bit just return faluse since the link can not be blocked
424 + * via this method.
425 + **/
426 +s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
427 +{
428 + u32 mmngc;
429 +
430 + DEBUGFUNC("ixgbe_check_reset_blocked");
431 +
432 + /* If we don't have this bit, it can't be blocking */
433 + if (hw->mac.type == ixgbe_mac_82598EB)
434 + return FALSE;
435 +
436 + mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
437 + if (mmngc & IXGBE_MMNGC_MNG_VETO) {
438 + ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
439 + "MNG_VETO bit detected.\n");
440 + return TRUE;
441 + }
442 +
443 + return FALSE;
444 +}
445 +
446 +/**
135 447 * ixgbe_validate_phy_addr - Determines phy address is valid
136 448 * @hw: pointer to hardware structure
137 449 *
138 450 **/
139 451 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
140 452 {
141 453 u16 phy_id = 0;
142 454 bool valid = FALSE;
143 455
144 456 DEBUGFUNC("ixgbe_validate_phy_addr");
145 457
146 458 hw->phy.addr = phy_addr;
147 459 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
148 460 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
149 461
150 462 if (phy_id != 0xFFFF && phy_id != 0x0)
151 463 valid = TRUE;
152 464
153 465 return valid;
154 466 }
155 467
156 468 /**
157 469 * ixgbe_get_phy_id - Get the phy type
158 470 * @hw: pointer to hardware structure
159 471 *
160 472 **/
161 473 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
162 474 {
163 475 u32 status;
164 476 u16 phy_id_high = 0;
165 477 u16 phy_id_low = 0;
166 478
167 479 DEBUGFUNC("ixgbe_get_phy_id");
168 480
169 481 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
170 482 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 483 &phy_id_high);
172 484
173 485 if (status == IXGBE_SUCCESS) {
174 486 hw->phy.id = (u32)(phy_id_high << 16);
175 487 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
176 488 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
177 489 &phy_id_low);
178 490 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
179 491 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
180 492 }
181 493 return status;
182 494 }
183 495
184 496 /**
185 497 * ixgbe_get_phy_type_from_id - Get the phy type
186 498 * @hw: pointer to hardware structure
187 499 *
188 500 **/
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189 501 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
190 502 {
191 503 enum ixgbe_phy_type phy_type;
192 504
193 505 DEBUGFUNC("ixgbe_get_phy_type_from_id");
194 506
195 507 switch (phy_id) {
196 508 case TN1010_PHY_ID:
197 509 phy_type = ixgbe_phy_tn;
198 510 break;
511 + case X550_PHY_ID1:
512 + case X550_PHY_ID2:
513 + case X550_PHY_ID3:
199 514 case X540_PHY_ID:
200 515 phy_type = ixgbe_phy_aq;
201 516 break;
202 517 case QT2022_PHY_ID:
203 518 phy_type = ixgbe_phy_qt;
204 519 break;
205 520 case ATH_PHY_ID:
206 521 phy_type = ixgbe_phy_nl;
207 522 break;
523 + case X557_PHY_ID:
524 + phy_type = ixgbe_phy_x550em_ext_t;
525 + break;
208 526 default:
209 527 phy_type = ixgbe_phy_unknown;
210 528 break;
211 529 }
212 530
213 531 DEBUGOUT1("phy type found is %d\n", phy_type);
214 532 return phy_type;
215 533 }
216 534
217 535 /**
218 536 * ixgbe_reset_phy_generic - Performs a PHY reset
219 537 * @hw: pointer to hardware structure
220 538 **/
221 539 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
222 540 {
223 541 u32 i;
224 542 u16 ctrl = 0;
225 543 s32 status = IXGBE_SUCCESS;
226 544
227 545 DEBUGFUNC("ixgbe_reset_phy_generic");
228 546
229 547 if (hw->phy.type == ixgbe_phy_unknown)
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230 548 status = ixgbe_identify_phy_generic(hw);
231 549
232 550 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
233 551 goto out;
234 552
235 553 /* Don't reset PHY if it's shut down due to overtemp. */
236 554 if (!hw->phy.reset_if_overtemp &&
237 555 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
238 556 goto out;
239 557
558 + /* Blocked by MNG FW so bail */
559 + if (ixgbe_check_reset_blocked(hw))
560 + goto out;
561 +
240 562 /*
241 563 * Perform soft PHY reset to the PHY_XS.
242 564 * This will cause a soft reset to the PHY
243 565 */
244 566 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
245 567 IXGBE_MDIO_PHY_XS_DEV_TYPE,
246 568 IXGBE_MDIO_PHY_XS_RESET);
247 569
248 570 /*
249 571 * Poll for reset bit to self-clear indicating reset is complete.
250 572 * Some PHYs could take up to 3 seconds to complete and need about
251 573 * 1.7 usec delay after the reset is complete.
252 574 */
253 575 for (i = 0; i < 30; i++) {
254 576 msec_delay(100);
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255 577 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
256 578 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
257 579 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
258 580 usec_delay(2);
259 581 break;
260 582 }
261 583 }
262 584
263 585 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
264 586 status = IXGBE_ERR_RESET_FAILED;
265 - DEBUGOUT("PHY reset polling failed to complete.\n");
587 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
588 + "PHY reset polling failed to complete.\n");
266 589 }
267 590
268 591 out:
269 592 return status;
270 593 }
271 594
272 595 /**
273 - * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
596 + * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
597 + * the SWFW lock
274 598 * @hw: pointer to hardware structure
275 599 * @reg_addr: 32 bit address of PHY register to read
276 600 * @phy_data: Pointer to read data from PHY register
277 601 **/
278 -s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
279 - u32 device_type, u16 *phy_data)
602 +s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
603 + u16 *phy_data)
280 604 {
281 - u32 command;
282 - u32 i;
283 - u32 data;
284 - s32 status = IXGBE_SUCCESS;
285 - u16 gssr;
605 + u32 i, data, command;
286 606
287 - DEBUGFUNC("ixgbe_read_phy_reg_generic");
607 + /* Setup and write the address cycle command */
608 + command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
609 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
610 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
611 + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
288 612
289 - if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
290 - gssr = IXGBE_GSSR_PHY1_SM;
291 - else
292 - gssr = IXGBE_GSSR_PHY0_SM;
613 + IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
293 614
294 - if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
295 - status = IXGBE_ERR_SWFW_SYNC;
615 + /*
616 + * Check every 10 usec to see if the address cycle completed.
617 + * The MDI Command bit will clear when the operation is
618 + * complete
619 + */
620 + for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
621 + usec_delay(10);
296 622
297 - if (status == IXGBE_SUCCESS) {
298 - /* Setup and write the address cycle command */
299 - command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
300 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
301 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
302 - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
623 + command = IXGBE_READ_REG(hw, IXGBE_MSCA);
624 + if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
625 + break;
626 + }
303 627
304 - IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
305 628
306 - /*
307 - * Check every 10 usec to see if the address cycle completed.
308 - * The MDI Command bit will clear when the operation is
309 - * complete
310 - */
311 - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
312 - usec_delay(10);
629 + if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
630 + ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
631 + return IXGBE_ERR_PHY;
632 + }
313 633
314 - command = IXGBE_READ_REG(hw, IXGBE_MSCA);
634 + /*
635 + * Address cycle complete, setup and write the read
636 + * command
637 + */
638 + command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
639 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
640 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
641 + (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
315 642
316 - if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
317 - break;
318 - }
643 + IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
319 644
320 - if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
321 - DEBUGOUT("PHY address command did not complete.\n");
322 - status = IXGBE_ERR_PHY;
323 - }
645 + /*
646 + * Check every 10 usec to see if the address cycle
647 + * completed. The MDI Command bit will clear when the
648 + * operation is complete
649 + */
650 + for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
651 + usec_delay(10);
324 652
325 - if (status == IXGBE_SUCCESS) {
326 - /*
327 - * Address cycle complete, setup and write the read
328 - * command
329 - */
330 - command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
331 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
332 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
333 - (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
653 + command = IXGBE_READ_REG(hw, IXGBE_MSCA);
654 + if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
655 + break;
656 + }
334 657
335 - IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
658 + if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
659 + ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
660 + return IXGBE_ERR_PHY;
661 + }
336 662
337 - /*
338 - * Check every 10 usec to see if the address cycle
339 - * completed. The MDI Command bit will clear when the
340 - * operation is complete
341 - */
342 - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
343 - usec_delay(10);
663 + /*
664 + * Read operation is complete. Get the data
665 + * from MSRWD
666 + */
667 + data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
668 + data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
669 + *phy_data = (u16)(data);
344 670
345 - command = IXGBE_READ_REG(hw, IXGBE_MSCA);
671 + return IXGBE_SUCCESS;
672 +}
346 673
347 - if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
348 - break;
349 - }
674 +/**
675 + * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
676 + * using the SWFW lock - this function is needed in most cases
677 + * @hw: pointer to hardware structure
678 + * @reg_addr: 32 bit address of PHY register to read
679 + * @phy_data: Pointer to read data from PHY register
680 + **/
681 +s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
682 + u32 device_type, u16 *phy_data)
683 +{
684 + s32 status;
685 + u32 gssr = hw->phy.phy_semaphore_mask;
350 686
351 - if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
352 - DEBUGOUT("PHY read command didn't complete\n");
353 - status = IXGBE_ERR_PHY;
354 - } else {
355 - /*
356 - * Read operation is complete. Get the data
357 - * from MSRWD
358 - */
359 - data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
360 - data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
361 - *phy_data = (u16)(data);
362 - }
363 - }
687 + DEBUGFUNC("ixgbe_read_phy_reg_generic");
364 688
689 + if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
690 + status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
691 + phy_data);
365 692 hw->mac.ops.release_swfw_sync(hw, gssr);
693 + } else {
694 + status = IXGBE_ERR_SWFW_SYNC;
366 695 }
367 696
368 697 return status;
369 698 }
370 699
371 700 /**
372 - * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
701 + * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
702 + * without SWFW lock
373 703 * @hw: pointer to hardware structure
374 704 * @reg_addr: 32 bit PHY register to write
375 705 * @device_type: 5 bit device type
376 706 * @phy_data: Data to write to the PHY register
377 707 **/
378 -s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
708 +s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
379 709 u32 device_type, u16 phy_data)
380 710 {
381 - u32 command;
382 - u32 i;
383 - s32 status = IXGBE_SUCCESS;
384 - u16 gssr;
711 + u32 i, command;
385 712
386 - DEBUGFUNC("ixgbe_write_phy_reg_generic");
713 + /* Put the data in the MDI single read and write data register*/
714 + IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
387 715
388 - if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
389 - gssr = IXGBE_GSSR_PHY1_SM;
390 - else
391 - gssr = IXGBE_GSSR_PHY0_SM;
716 + /* Setup and write the address cycle command */
717 + command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
718 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
719 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
720 + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
392 721
393 - if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
394 - status = IXGBE_ERR_SWFW_SYNC;
722 + IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
395 723
396 - if (status == IXGBE_SUCCESS) {
397 - /* Put the data in the MDI single read and write data register*/
398 - IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
724 + /*
725 + * Check every 10 usec to see if the address cycle completed.
726 + * The MDI Command bit will clear when the operation is
727 + * complete
728 + */
729 + for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
730 + usec_delay(10);
399 731
400 - /* Setup and write the address cycle command */
401 - command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
402 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
403 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
404 - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
732 + command = IXGBE_READ_REG(hw, IXGBE_MSCA);
733 + if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
734 + break;
735 + }
405 736
406 - IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
737 + if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
738 + ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
739 + return IXGBE_ERR_PHY;
740 + }
407 741
408 - /*
409 - * Check every 10 usec to see if the address cycle completed.
410 - * The MDI Command bit will clear when the operation is
411 - * complete
412 - */
413 - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
414 - usec_delay(10);
742 + /*
743 + * Address cycle complete, setup and write the write
744 + * command
745 + */
746 + command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
747 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
748 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
749 + (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
415 750
416 - command = IXGBE_READ_REG(hw, IXGBE_MSCA);
751 + IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
417 752
418 - if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
419 - break;
420 - }
753 + /*
754 + * Check every 10 usec to see if the address cycle
755 + * completed. The MDI Command bit will clear when the
756 + * operation is complete
757 + */
758 + for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
759 + usec_delay(10);
421 760
422 - if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
423 - DEBUGOUT("PHY address cmd didn't complete\n");
424 - status = IXGBE_ERR_PHY;
425 - }
761 + command = IXGBE_READ_REG(hw, IXGBE_MSCA);
762 + if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
763 + break;
764 + }
426 765
427 - if (status == IXGBE_SUCCESS) {
428 - /*
429 - * Address cycle complete, setup and write the write
430 - * command
431 - */
432 - command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
433 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
434 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
435 - (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
766 + if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
767 + ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
768 + return IXGBE_ERR_PHY;
769 + }
436 770
437 - IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
771 + return IXGBE_SUCCESS;
772 +}
438 773
439 - /*
440 - * Check every 10 usec to see if the address cycle
441 - * completed. The MDI Command bit will clear when the
442 - * operation is complete
443 - */
444 - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
445 - usec_delay(10);
774 +/**
775 + * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
776 + * using SWFW lock- this function is needed in most cases
777 + * @hw: pointer to hardware structure
778 + * @reg_addr: 32 bit PHY register to write
779 + * @device_type: 5 bit device type
780 + * @phy_data: Data to write to the PHY register
781 + **/
782 +s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
783 + u32 device_type, u16 phy_data)
784 +{
785 + s32 status;
786 + u32 gssr = hw->phy.phy_semaphore_mask;
446 787
447 - command = IXGBE_READ_REG(hw, IXGBE_MSCA);
788 + DEBUGFUNC("ixgbe_write_phy_reg_generic");
448 789
449 - if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
450 - break;
451 - }
452 -
453 - if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 - DEBUGOUT("PHY address cmd didn't complete\n");
455 - status = IXGBE_ERR_PHY;
456 - }
457 - }
458 -
790 + if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
791 + status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
792 + phy_data);
459 793 hw->mac.ops.release_swfw_sync(hw, gssr);
794 + } else {
795 + status = IXGBE_ERR_SWFW_SYNC;
460 796 }
461 797
462 798 return status;
463 799 }
464 800
465 801 /**
466 - * ixgbe_setup_phy_link_generic - Set and restart autoneg
802 + * ixgbe_setup_phy_link_generic - Set and restart auto-neg
467 803 * @hw: pointer to hardware structure
468 804 *
469 - * Restart autonegotiation and PHY and waits for completion.
805 + * Restart auto-negotiation and PHY and waits for completion.
470 806 **/
471 807 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 808 {
473 - s32 status;
474 - u32 time_out;
475 - u32 max_time_out = 10;
809 + s32 status = IXGBE_SUCCESS;
476 810 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 811 bool autoneg = FALSE;
478 812 ixgbe_link_speed speed;
479 813
480 814 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481 815
482 - status =
483 - ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484 - if (status != IXGBE_SUCCESS)
485 - return status;
816 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
486 817
487 818 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
488 819 /* Set or unset auto-negotiation 10G advertisement */
489 820 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
490 821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 822 &autoneg_reg);
492 823
493 824 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
494 825 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
495 826 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
496 827
497 828 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
498 829 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
499 830 autoneg_reg);
500 831 }
501 832
833 + if (hw->mac.type == ixgbe_mac_X550) {
834 + if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
835 + /* Set or unset auto-negotiation 5G advertisement */
836 + hw->phy.ops.read_reg(hw,
837 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
838 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
839 + &autoneg_reg);
840 +
841 + autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
842 + if (hw->phy.autoneg_advertised &
843 + IXGBE_LINK_SPEED_5GB_FULL)
844 + autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
845 +
846 + hw->phy.ops.write_reg(hw,
847 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
848 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
849 + autoneg_reg);
850 + }
851 +
852 + if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
853 + /* Set or unset auto-negotiation 2.5G advertisement */
854 + hw->phy.ops.read_reg(hw,
855 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
856 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
857 + &autoneg_reg);
858 +
859 + autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
860 + if (hw->phy.autoneg_advertised &
861 + IXGBE_LINK_SPEED_2_5GB_FULL)
862 + autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
863 +
864 + hw->phy.ops.write_reg(hw,
865 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
866 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
867 + autoneg_reg);
868 + }
869 + }
870 +
502 871 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
503 872 /* Set or unset auto-negotiation 1G advertisement */
504 873 hw->phy.ops.read_reg(hw,
505 874 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
506 875 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 876 &autoneg_reg);
508 877
509 878 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
510 879 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
511 880 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
512 881
513 882 hw->phy.ops.write_reg(hw,
514 883 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
515 884 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
516 885 autoneg_reg);
517 886 }
518 887
519 888 if (speed & IXGBE_LINK_SPEED_100_FULL) {
520 889 /* Set or unset auto-negotiation 100M advertisement */
521 890 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
522 891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
523 892 &autoneg_reg);
524 893
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525 894 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
526 895 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
527 896 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
528 897 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
529 898
530 899 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
531 900 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
532 901 autoneg_reg);
533 902 }
534 903
535 - /* Restart PHY autonegotiation and wait for completion */
904 + /* Blocked by MNG FW so don't reset PHY */
905 + if (ixgbe_check_reset_blocked(hw))
906 + return status;
907 +
908 + /* Restart PHY auto-negotiation. */
536 909 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
537 910 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
538 911
539 912 autoneg_reg |= IXGBE_MII_RESTART;
540 913
541 914 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
542 915 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
543 916
544 - /* Wait for autonegotiation to finish */
545 - for (time_out = 0; time_out < max_time_out; time_out++) {
546 - usec_delay(10);
547 - /* Restart PHY autonegotiation and wait for completion */
548 - status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
549 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 - &autoneg_reg);
551 -
552 - autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
553 - if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
554 - break;
555 - }
556 -
557 - if (time_out == max_time_out) {
558 - status = IXGBE_ERR_LINK_SETUP;
559 - DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
560 - }
561 -
562 917 return status;
563 918 }
564 919
565 920 /**
566 921 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
567 922 * @hw: pointer to hardware structure
568 923 * @speed: new link speed
569 - * @autoneg: TRUE if autonegotiation enabled
570 924 **/
571 925 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
572 926 ixgbe_link_speed speed,
573 - bool autoneg,
574 927 bool autoneg_wait_to_complete)
575 928 {
576 - UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
929 + UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
577 930
578 931 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
579 932
580 933 /*
581 934 * Clear autoneg_advertised and set new values based on input link
582 935 * speed.
583 936 */
584 937 hw->phy.autoneg_advertised = 0;
585 938
586 939 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
587 940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
588 941
942 + if (speed & IXGBE_LINK_SPEED_5GB_FULL)
943 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
944 +
945 + if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
946 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
947 +
589 948 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
590 949 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
591 950
592 951 if (speed & IXGBE_LINK_SPEED_100_FULL)
593 952 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
594 953
595 954 /* Setup link based on the new speed settings */
596 - hw->phy.ops.setup_link(hw);
955 + ixgbe_setup_phy_link(hw);
597 956
598 957 return IXGBE_SUCCESS;
599 958 }
600 959
601 960 /**
961 + * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
962 + * @hw: pointer to hardware structure
963 + *
964 + * Determines the supported link capabilities by reading the PHY auto
965 + * negotiation register.
966 + **/
967 +static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
968 +{
969 + s32 status;
970 + u16 speed_ability;
971 +
972 + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
973 + IXGBE_MDIO_PMA_PMD_DEV_TYPE,
974 + &speed_ability);
975 + if (status)
976 + return status;
977 +
978 + if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
979 + hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
980 + if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
981 + hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
982 + if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
983 + hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
984 +
985 + switch (hw->mac.type) {
986 + case ixgbe_mac_X550:
987 + hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
988 + hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
989 + break;
990 + case ixgbe_mac_X550EM_x:
991 + hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
992 + break;
993 + default:
994 + break;
995 + }
996 +
997 + return status;
998 +}
999 +
1000 +/**
602 1001 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
603 1002 * @hw: pointer to hardware structure
604 1003 * @speed: pointer to link speed
605 1004 * @autoneg: boolean auto-negotiation value
606 - *
607 - * Determines the link capabilities by reading the AUTOC register.
608 1005 **/
609 1006 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
610 1007 ixgbe_link_speed *speed,
611 1008 bool *autoneg)
612 1009 {
613 - s32 status = IXGBE_ERR_LINK_SETUP;
614 - u16 speed_ability;
1010 + s32 status = IXGBE_SUCCESS;
615 1011
616 1012 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
617 1013
618 - *speed = 0;
619 1014 *autoneg = TRUE;
1015 + if (!hw->phy.speeds_supported)
1016 + status = ixgbe_get_copper_speeds_supported(hw);
620 1017
621 - status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
622 - IXGBE_MDIO_PMA_PMD_DEV_TYPE,
623 - &speed_ability);
624 -
625 - if (status == IXGBE_SUCCESS) {
626 - if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
627 - *speed |= IXGBE_LINK_SPEED_10GB_FULL;
628 - if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
629 - *speed |= IXGBE_LINK_SPEED_1GB_FULL;
630 - if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
631 - *speed |= IXGBE_LINK_SPEED_100_FULL;
632 - }
633 -
1018 + *speed = hw->phy.speeds_supported;
634 1019 return status;
635 1020 }
636 1021
637 1022 /**
638 1023 * ixgbe_check_phy_link_tnx - Determine link and speed status
639 1024 * @hw: pointer to hardware structure
640 1025 *
641 1026 * Reads the VS1 register to determine if link is up and the current speed for
642 1027 * the PHY.
643 1028 **/
644 1029 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
645 1030 bool *link_up)
646 1031 {
647 1032 s32 status = IXGBE_SUCCESS;
648 1033 u32 time_out;
649 1034 u32 max_time_out = 10;
650 1035 u16 phy_link = 0;
651 1036 u16 phy_speed = 0;
652 1037 u16 phy_data = 0;
653 1038
654 1039 DEBUGFUNC("ixgbe_check_phy_link_tnx");
655 1040
656 1041 /* Initialize speed and link to default case */
657 1042 *link_up = FALSE;
658 1043 *speed = IXGBE_LINK_SPEED_10GB_FULL;
659 1044
660 1045 /*
661 1046 * Check current speed and link status of the PHY register.
662 1047 * This is a vendor specific register and may have to
663 1048 * be changed for other copper PHYs.
664 1049 */
665 1050 for (time_out = 0; time_out < max_time_out; time_out++) {
666 1051 usec_delay(10);
667 1052 status = hw->phy.ops.read_reg(hw,
668 1053 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
669 1054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
670 1055 &phy_data);
671 1056 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
672 1057 phy_speed = phy_data &
673 1058 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 1059 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
675 1060 *link_up = TRUE;
676 1061 if (phy_speed ==
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677 1062 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 1063 *speed = IXGBE_LINK_SPEED_1GB_FULL;
679 1064 break;
680 1065 }
681 1066 }
682 1067
683 1068 return status;
684 1069 }
685 1070
686 1071 /**
687 - * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1072 + * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
688 1073 * @hw: pointer to hardware structure
689 1074 *
690 - * Restart autonegotiation and PHY and waits for completion.
1075 + * Restart auto-negotiation and PHY and waits for completion.
691 1076 **/
692 1077 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
693 1078 {
694 - s32 status;
695 - u32 time_out;
696 - u32 max_time_out = 10;
1079 + s32 status = IXGBE_SUCCESS;
697 1080 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 1081 bool autoneg = FALSE;
699 1082 ixgbe_link_speed speed;
700 1083
701 1084 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
702 1085
703 - status =
704 - ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
705 - if (status != IXGBE_SUCCESS)
706 - return status;
1086 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
707 1087
708 1088 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
709 1089 /* Set or unset auto-negotiation 10G advertisement */
710 1090 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
711 1091 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
712 1092 &autoneg_reg);
713 1093
714 1094 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
715 1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
716 1096 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
717 1097
718 1098 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
719 1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
720 1100 autoneg_reg);
721 1101 }
722 1102
723 1103 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
724 1104 /* Set or unset auto-negotiation 1G advertisement */
725 1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
726 1106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
727 1107 &autoneg_reg);
728 1108
729 1109 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
730 1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
731 1111 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
732 1112
733 1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
734 1114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
735 1115 autoneg_reg);
736 1116 }
737 1117
738 1118 if (speed & IXGBE_LINK_SPEED_100_FULL) {
739 1119 /* Set or unset auto-negotiation 100M advertisement */
740 1120 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
741 1121 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
742 1122 &autoneg_reg);
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743 1123
744 1124 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
745 1125 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
746 1126 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
747 1127
748 1128 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
749 1129 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
750 1130 autoneg_reg);
751 1131 }
752 1132
753 - /* Restart PHY autonegotiation and wait for completion */
1133 + /* Blocked by MNG FW so don't reset PHY */
1134 + if (ixgbe_check_reset_blocked(hw))
1135 + return status;
1136 +
1137 + /* Restart PHY auto-negotiation. */
754 1138 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
755 1139 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
756 1140
757 1141 autoneg_reg |= IXGBE_MII_RESTART;
758 1142
759 1143 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
760 1144 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
761 1145
762 - /* Wait for autonegotiation to finish */
763 - for (time_out = 0; time_out < max_time_out; time_out++) {
764 - usec_delay(10);
765 - /* Restart PHY autonegotiation and wait for completion */
766 - status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
767 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
768 - &autoneg_reg);
769 -
770 - autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
771 - if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
772 - break;
773 - }
774 -
775 - if (time_out == max_time_out) {
776 - status = IXGBE_ERR_LINK_SETUP;
777 - DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
778 - }
779 -
780 1146 return status;
781 1147 }
782 1148
783 1149 /**
784 1150 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
785 1151 * @hw: pointer to hardware structure
786 1152 * @firmware_version: pointer to the PHY Firmware Version
787 1153 **/
788 1154 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
789 1155 u16 *firmware_version)
790 1156 {
791 - s32 status = IXGBE_SUCCESS;
1157 + s32 status;
792 1158
793 1159 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
794 1160
795 1161 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
796 1162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
797 1163 firmware_version);
798 1164
799 1165 return status;
800 1166 }
801 1167
802 1168 /**
803 1169 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
804 1170 * @hw: pointer to hardware structure
805 1171 * @firmware_version: pointer to the PHY Firmware Version
806 1172 **/
807 1173 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
808 1174 u16 *firmware_version)
809 1175 {
810 - s32 status = IXGBE_SUCCESS;
1176 + s32 status;
811 1177
812 1178 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
813 1179
814 1180 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
815 1181 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
816 1182 firmware_version);
817 1183
818 1184 return status;
819 1185 }
820 1186
821 1187 /**
822 1188 * ixgbe_reset_phy_nl - Performs a PHY reset
823 1189 * @hw: pointer to hardware structure
824 1190 **/
825 1191 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
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826 1192 {
827 1193 u16 phy_offset, control, eword, edata, block_crc;
828 1194 bool end_data = FALSE;
829 1195 u16 list_offset, data_offset;
830 1196 u16 phy_data = 0;
831 1197 s32 ret_val = IXGBE_SUCCESS;
832 1198 u32 i;
833 1199
834 1200 DEBUGFUNC("ixgbe_reset_phy_nl");
835 1201
1202 + /* Blocked by MNG FW so bail */
1203 + if (ixgbe_check_reset_blocked(hw))
1204 + goto out;
1205 +
836 1206 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
837 1207 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
838 1208
839 1209 /* reset the PHY and poll for completion */
840 1210 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
841 1211 IXGBE_MDIO_PHY_XS_DEV_TYPE,
842 1212 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
843 1213
844 1214 for (i = 0; i < 100; i++) {
845 1215 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
846 1216 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
847 1217 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
848 1218 break;
849 1219 msec_delay(10);
850 1220 }
851 1221
852 1222 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
853 1223 DEBUGOUT("PHY reset did not complete.\n");
854 1224 ret_val = IXGBE_ERR_PHY;
855 1225 goto out;
856 1226 }
857 1227
858 1228 /* Get init offsets */
859 1229 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
860 1230 &data_offset);
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861 1231 if (ret_val != IXGBE_SUCCESS)
862 1232 goto out;
863 1233
864 1234 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
865 1235 data_offset++;
866 1236 while (!end_data) {
867 1237 /*
868 1238 * Read control word from PHY init contents offset
869 1239 */
870 1240 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1241 + if (ret_val)
1242 + goto err_eeprom;
871 1243 control = (eword & IXGBE_CONTROL_MASK_NL) >>
872 1244 IXGBE_CONTROL_SHIFT_NL;
873 1245 edata = eword & IXGBE_DATA_MASK_NL;
874 1246 switch (control) {
875 1247 case IXGBE_DELAY_NL:
876 1248 data_offset++;
877 1249 DEBUGOUT1("DELAY: %d MS\n", edata);
878 1250 msec_delay(edata);
879 1251 break;
880 1252 case IXGBE_DATA_NL:
881 1253 DEBUGOUT("DATA:\n");
882 1254 data_offset++;
883 - hw->eeprom.ops.read(hw, data_offset++,
884 - &phy_offset);
1255 + ret_val = hw->eeprom.ops.read(hw, data_offset,
1256 + &phy_offset);
1257 + if (ret_val)
1258 + goto err_eeprom;
1259 + data_offset++;
885 1260 for (i = 0; i < edata; i++) {
886 - hw->eeprom.ops.read(hw, data_offset, &eword);
1261 + ret_val = hw->eeprom.ops.read(hw, data_offset,
1262 + &eword);
1263 + if (ret_val)
1264 + goto err_eeprom;
887 1265 hw->phy.ops.write_reg(hw, phy_offset,
888 1266 IXGBE_TWINAX_DEV, eword);
889 1267 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
890 1268 phy_offset);
891 1269 data_offset++;
892 1270 phy_offset++;
893 1271 }
894 1272 break;
895 1273 case IXGBE_CONTROL_NL:
896 1274 data_offset++;
897 1275 DEBUGOUT("CONTROL:\n");
898 1276 if (edata == IXGBE_CONTROL_EOL_NL) {
899 1277 DEBUGOUT("EOL\n");
900 1278 end_data = TRUE;
901 1279 } else if (edata == IXGBE_CONTROL_SOL_NL) {
902 1280 DEBUGOUT("SOL\n");
903 1281 } else {
904 1282 DEBUGOUT("Bad control value\n");
905 1283 ret_val = IXGBE_ERR_PHY;
906 1284 goto out;
907 1285 }
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908 1286 break;
909 1287 default:
910 1288 DEBUGOUT("Bad control type\n");
911 1289 ret_val = IXGBE_ERR_PHY;
912 1290 goto out;
913 1291 }
914 1292 }
915 1293
916 1294 out:
917 1295 return ret_val;
1296 +
1297 +err_eeprom:
1298 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1299 + "eeprom read at offset %d failed", data_offset);
1300 + return IXGBE_ERR_PHY;
918 1301 }
919 1302
920 1303 /**
921 1304 * ixgbe_identify_module_generic - Identifies module type
922 1305 * @hw: pointer to hardware structure
923 1306 *
924 1307 * Determines HW type and calls appropriate function.
925 1308 **/
926 1309 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
927 1310 {
928 1311 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
929 1312
930 1313 DEBUGFUNC("ixgbe_identify_module_generic");
931 1314
932 1315 switch (hw->mac.ops.get_media_type(hw)) {
933 1316 case ixgbe_media_type_fiber:
934 1317 status = ixgbe_identify_sfp_module_generic(hw);
935 1318 break;
936 1319
1320 + case ixgbe_media_type_fiber_qsfp:
1321 + status = ixgbe_identify_qsfp_module_generic(hw);
1322 + break;
937 1323
938 1324 default:
939 1325 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
940 1326 status = IXGBE_ERR_SFP_NOT_PRESENT;
941 1327 break;
942 1328 }
943 1329
944 1330 return status;
945 1331 }
946 1332
947 1333 /**
948 1334 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
949 1335 * @hw: pointer to hardware structure
950 1336 *
951 1337 * Searches for and identifies the SFP module and assigns appropriate PHY type.
952 1338 **/
953 1339 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
954 1340 {
955 1341 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
956 1342 u32 vendor_oui = 0;
957 1343 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
958 1344 u8 identifier = 0;
959 1345 u8 comp_codes_1g = 0;
960 1346 u8 comp_codes_10g = 0;
961 1347 u8 oui_bytes[3] = {0, 0, 0};
962 1348 u8 cable_tech = 0;
963 1349 u8 cable_spec = 0;
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964 1350 u16 enforce_sfp = 0;
965 1351
966 1352 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
967 1353
968 1354 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
969 1355 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
970 1356 status = IXGBE_ERR_SFP_NOT_PRESENT;
971 1357 goto out;
972 1358 }
973 1359
1360 + /* LAN ID is needed for I2C access */
1361 + hw->mac.ops.set_lan_id(hw);
1362 +
974 1363 status = hw->phy.ops.read_i2c_eeprom(hw,
975 1364 IXGBE_SFF_IDENTIFIER,
976 1365 &identifier);
977 1366
978 - if (status == IXGBE_ERR_SWFW_SYNC ||
979 - status == IXGBE_ERR_I2C ||
980 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1367 + if (status != IXGBE_SUCCESS)
981 1368 goto err_read_i2c_eeprom;
982 1369
983 - /* LAN ID is needed for sfp_type determination */
984 - hw->mac.ops.set_lan_id(hw);
985 -
986 1370 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
987 1371 hw->phy.type = ixgbe_phy_sfp_unsupported;
988 1372 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
989 1373 } else {
990 1374 status = hw->phy.ops.read_i2c_eeprom(hw,
991 1375 IXGBE_SFF_1GBE_COMP_CODES,
992 1376 &comp_codes_1g);
993 1377
994 - if (status == IXGBE_ERR_SWFW_SYNC ||
995 - status == IXGBE_ERR_I2C ||
996 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1378 + if (status != IXGBE_SUCCESS)
997 1379 goto err_read_i2c_eeprom;
998 1380
999 1381 status = hw->phy.ops.read_i2c_eeprom(hw,
1000 1382 IXGBE_SFF_10GBE_COMP_CODES,
1001 1383 &comp_codes_10g);
1002 1384
1003 - if (status == IXGBE_ERR_SWFW_SYNC ||
1004 - status == IXGBE_ERR_I2C ||
1005 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1385 + if (status != IXGBE_SUCCESS)
1006 1386 goto err_read_i2c_eeprom;
1007 1387 status = hw->phy.ops.read_i2c_eeprom(hw,
1008 1388 IXGBE_SFF_CABLE_TECHNOLOGY,
1009 1389 &cable_tech);
1010 1390
1011 - if (status == IXGBE_ERR_SWFW_SYNC ||
1012 - status == IXGBE_ERR_I2C ||
1013 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1391 + if (status != IXGBE_SUCCESS)
1014 1392 goto err_read_i2c_eeprom;
1015 1393
1016 1394 /* ID Module
1017 1395 * =========
1018 1396 * 0 SFP_DA_CU
1019 1397 * 1 SFP_SR
1020 1398 * 2 SFP_LR
1021 1399 * 3 SFP_DA_CORE0 - 82599-specific
1022 1400 * 4 SFP_DA_CORE1 - 82599-specific
1023 1401 * 5 SFP_SR/LR_CORE0 - 82599-specific
1024 1402 * 6 SFP_SR/LR_CORE1 - 82599-specific
1025 1403 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1026 1404 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1027 1405 * 9 SFP_1g_cu_CORE0 - 82599-specific
1028 1406 * 10 SFP_1g_cu_CORE1 - 82599-specific
1029 1407 * 11 SFP_1g_sx_CORE0 - 82599-specific
1030 1408 * 12 SFP_1g_sx_CORE1 - 82599-specific
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1031 1409 */
1032 1410 if (hw->mac.type == ixgbe_mac_82598EB) {
1033 1411 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1034 1412 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1035 1413 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1036 1414 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1037 1415 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1038 1416 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1039 1417 else
1040 1418 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1041 - } else if (hw->mac.type == ixgbe_mac_82599EB) {
1419 + } else {
1042 1420 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1043 1421 if (hw->bus.lan_id == 0)
1044 1422 hw->phy.sfp_type =
1045 1423 ixgbe_sfp_type_da_cu_core0;
1046 1424 else
1047 1425 hw->phy.sfp_type =
1048 1426 ixgbe_sfp_type_da_cu_core1;
1049 1427 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1050 1428 hw->phy.ops.read_i2c_eeprom(
1051 1429 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1052 1430 &cable_spec);
1053 1431 if (cable_spec &
1054 1432 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1055 1433 if (hw->bus.lan_id == 0)
1056 1434 hw->phy.sfp_type =
1057 1435 ixgbe_sfp_type_da_act_lmt_core0;
1058 1436 else
1059 1437 hw->phy.sfp_type =
1060 1438 ixgbe_sfp_type_da_act_lmt_core1;
1061 1439 } else {
1062 1440 hw->phy.sfp_type =
1063 1441 ixgbe_sfp_type_unknown;
1064 1442 }
1065 1443 } else if (comp_codes_10g &
1066 1444 (IXGBE_SFF_10GBASESR_CAPABLE |
1067 1445 IXGBE_SFF_10GBASELR_CAPABLE)) {
1068 1446 if (hw->bus.lan_id == 0)
1069 1447 hw->phy.sfp_type =
1070 1448 ixgbe_sfp_type_srlr_core0;
1071 1449 else
1072 1450 hw->phy.sfp_type =
1073 1451 ixgbe_sfp_type_srlr_core1;
1074 1452 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1075 1453 if (hw->bus.lan_id == 0)
1076 1454 hw->phy.sfp_type =
1077 1455 ixgbe_sfp_type_1g_cu_core0;
1078 1456 else
1079 1457 hw->phy.sfp_type =
1080 1458 ixgbe_sfp_type_1g_cu_core1;
1081 1459 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1082 1460 if (hw->bus.lan_id == 0)
1083 1461 hw->phy.sfp_type =
1084 1462 ixgbe_sfp_type_1g_sx_core0;
1085 1463 else
1086 1464 hw->phy.sfp_type =
1087 1465 ixgbe_sfp_type_1g_sx_core1;
1088 1466 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1089 1467 if (hw->bus.lan_id == 0)
1090 1468 hw->phy.sfp_type =
1091 1469 ixgbe_sfp_type_1g_lx_core0;
1092 1470 else
1093 1471 hw->phy.sfp_type =
1094 1472 ixgbe_sfp_type_1g_lx_core1;
1095 1473 } else {
1096 1474 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1097 1475 }
1098 1476 }
1099 1477
1100 1478 if (hw->phy.sfp_type != stored_sfp_type)
1101 1479 hw->phy.sfp_setup_needed = TRUE;
1102 1480
1103 1481 /* Determine if the SFP+ PHY is dual speed or not. */
1104 1482 hw->phy.multispeed_fiber = FALSE;
1105 1483 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1106 1484 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1107 1485 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
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1108 1486 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1109 1487 hw->phy.multispeed_fiber = TRUE;
1110 1488
1111 1489 /* Determine PHY vendor */
1112 1490 if (hw->phy.type != ixgbe_phy_nl) {
1113 1491 hw->phy.id = identifier;
1114 1492 status = hw->phy.ops.read_i2c_eeprom(hw,
1115 1493 IXGBE_SFF_VENDOR_OUI_BYTE0,
1116 1494 &oui_bytes[0]);
1117 1495
1118 - if (status == IXGBE_ERR_SWFW_SYNC ||
1119 - status == IXGBE_ERR_I2C ||
1120 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1496 + if (status != IXGBE_SUCCESS)
1121 1497 goto err_read_i2c_eeprom;
1122 1498
1123 1499 status = hw->phy.ops.read_i2c_eeprom(hw,
1124 1500 IXGBE_SFF_VENDOR_OUI_BYTE1,
1125 1501 &oui_bytes[1]);
1126 1502
1127 - if (status == IXGBE_ERR_SWFW_SYNC ||
1128 - status == IXGBE_ERR_I2C ||
1129 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1503 + if (status != IXGBE_SUCCESS)
1130 1504 goto err_read_i2c_eeprom;
1131 1505
1132 1506 status = hw->phy.ops.read_i2c_eeprom(hw,
1133 1507 IXGBE_SFF_VENDOR_OUI_BYTE2,
1134 1508 &oui_bytes[2]);
1135 1509
1136 - if (status == IXGBE_ERR_SWFW_SYNC ||
1137 - status == IXGBE_ERR_I2C ||
1138 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1510 + if (status != IXGBE_SUCCESS)
1139 1511 goto err_read_i2c_eeprom;
1140 1512
1141 1513 vendor_oui =
1142 1514 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1143 1515 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1144 1516 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1145 1517
1146 1518 switch (vendor_oui) {
1147 1519 case IXGBE_SFF_VENDOR_OUI_TYCO:
1148 1520 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1149 1521 hw->phy.type =
1150 1522 ixgbe_phy_sfp_passive_tyco;
1151 1523 break;
1152 1524 case IXGBE_SFF_VENDOR_OUI_FTL:
1153 1525 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1154 1526 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1155 1527 else
1156 1528 hw->phy.type = ixgbe_phy_sfp_ftl;
1157 1529 break;
1158 1530 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1159 1531 hw->phy.type = ixgbe_phy_sfp_avago;
1160 1532 break;
1161 1533 case IXGBE_SFF_VENDOR_OUI_INTEL:
1162 1534 hw->phy.type = ixgbe_phy_sfp_intel;
1163 1535 break;
1164 1536 default:
1165 1537 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1166 1538 hw->phy.type =
1167 1539 ixgbe_phy_sfp_passive_unknown;
1168 1540 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1169 1541 hw->phy.type =
1170 1542 ixgbe_phy_sfp_active_unknown;
1171 1543 else
1172 1544 hw->phy.type = ixgbe_phy_sfp_unknown;
1173 1545 break;
1174 1546 }
1175 1547 }
1176 1548
1177 1549 /* Allow any DA cable vendor */
1178 1550 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1179 1551 IXGBE_SFF_DA_ACTIVE_CABLE)) {
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1180 1552 status = IXGBE_SUCCESS;
1181 1553 goto out;
1182 1554 }
1183 1555
1184 1556 /* Verify supported 1G SFP modules */
1185 1557 if (comp_codes_10g == 0 &&
1186 1558 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1187 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1188 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1189 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1190 - hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1562 + hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1191 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1192 1564 hw->phy.type = ixgbe_phy_sfp_unsupported;
1193 1565 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1194 1566 goto out;
1195 1567 }
1196 1568
1197 1569 /* Anything else 82598-based is supported */
1198 1570 if (hw->mac.type == ixgbe_mac_82598EB) {
1199 1571 status = IXGBE_SUCCESS;
1200 1572 goto out;
1201 1573 }
1202 1574
1203 - (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1575 + ixgbe_get_device_caps(hw, &enforce_sfp);
1204 1576 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1205 1577 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1206 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1207 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1208 1580 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1209 1581 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210 1582 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1211 1583 /* Make sure we're a supported PHY type */
1212 1584 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1213 1585 status = IXGBE_SUCCESS;
1214 1586 } else {
1215 1587 if (hw->allow_unsupported_sfp == TRUE) {
1216 1588 EWARN(hw, "WARNING: Intel (R) Network "
1217 1589 "Connections are quality tested "
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1218 1590 "using Intel (R) Ethernet Optics."
1219 1591 " Using untested modules is not "
1220 1592 "supported and may cause unstable"
1221 1593 " operation or damage to the "
1222 1594 "module or the adapter. Intel "
1223 1595 "Corporation is not responsible "
1224 1596 "for any harm caused by using "
1225 1597 "untested modules.\n", status);
1226 1598 status = IXGBE_SUCCESS;
1227 1599 } else {
1228 - EWARN(hw, "SFP+ module not supported\n",
1229 - status);
1600 + DEBUGOUT("SFP+ module not supported\n");
1230 1601 hw->phy.type =
1231 1602 ixgbe_phy_sfp_unsupported;
1232 1603 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1233 1604 }
1234 1605 }
1235 1606 } else {
1236 1607 status = IXGBE_SUCCESS;
1237 1608 }
1238 1609 }
1239 1610
1240 1611 out:
1241 1612 return status;
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1242 1613
1243 1614 err_read_i2c_eeprom:
1244 1615 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1245 1616 if (hw->phy.type != ixgbe_phy_nl) {
1246 1617 hw->phy.id = 0;
1247 1618 hw->phy.type = ixgbe_phy_unknown;
1248 1619 }
1249 1620 return IXGBE_ERR_SFP_NOT_PRESENT;
1250 1621 }
1251 1622
1623 +/**
1624 + * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1625 + * @hw: pointer to hardware structure
1626 + *
1627 + * Determines physical layer capabilities of the current SFP.
1628 + */
1629 +s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1630 +{
1631 + u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1632 + u8 comp_codes_10g = 0;
1633 + u8 comp_codes_1g = 0;
1252 1634
1635 + DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1253 1636
1637 + hw->phy.ops.identify_sfp(hw);
1638 + if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1639 + return physical_layer;
1640 +
1641 + switch (hw->phy.type) {
1642 + case ixgbe_phy_sfp_passive_tyco:
1643 + case ixgbe_phy_sfp_passive_unknown:
1644 + case ixgbe_phy_qsfp_passive_unknown:
1645 + physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1646 + break;
1647 + case ixgbe_phy_sfp_ftl_active:
1648 + case ixgbe_phy_sfp_active_unknown:
1649 + case ixgbe_phy_qsfp_active_unknown:
1650 + physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1651 + break;
1652 + case ixgbe_phy_sfp_avago:
1653 + case ixgbe_phy_sfp_ftl:
1654 + case ixgbe_phy_sfp_intel:
1655 + case ixgbe_phy_sfp_unknown:
1656 + hw->phy.ops.read_i2c_eeprom(hw,
1657 + IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1658 + hw->phy.ops.read_i2c_eeprom(hw,
1659 + IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1660 + if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1661 + physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1662 + else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1663 + physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1664 + else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1665 + physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1666 + else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1667 + physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1668 + break;
1669 + case ixgbe_phy_qsfp_intel:
1670 + case ixgbe_phy_qsfp_unknown:
1671 + hw->phy.ops.read_i2c_eeprom(hw,
1672 + IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1673 + if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1674 + physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1675 + else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1676 + physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1677 + break;
1678 + default:
1679 + break;
1680 + }
1681 +
1682 + return physical_layer;
1683 +}
1684 +
1254 1685 /**
1686 + * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1687 + * @hw: pointer to hardware structure
1688 + *
1689 + * Searches for and identifies the QSFP module and assigns appropriate PHY type
1690 + **/
1691 +s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1692 +{
1693 + s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1694 + u32 vendor_oui = 0;
1695 + enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1696 + u8 identifier = 0;
1697 + u8 comp_codes_1g = 0;
1698 + u8 comp_codes_10g = 0;
1699 + u8 oui_bytes[3] = {0, 0, 0};
1700 + u16 enforce_sfp = 0;
1701 + u8 connector = 0;
1702 + u8 cable_length = 0;
1703 + u8 device_tech = 0;
1704 + bool active_cable = FALSE;
1705 +
1706 + DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1707 +
1708 + if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1709 + hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1710 + status = IXGBE_ERR_SFP_NOT_PRESENT;
1711 + goto out;
1712 + }
1713 +
1714 + /* LAN ID is needed for I2C access */
1715 + hw->mac.ops.set_lan_id(hw);
1716 +
1717 + status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1718 + &identifier);
1719 +
1720 + if (status != IXGBE_SUCCESS)
1721 + goto err_read_i2c_eeprom;
1722 +
1723 + if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1724 + hw->phy.type = ixgbe_phy_sfp_unsupported;
1725 + status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1726 + goto out;
1727 + }
1728 +
1729 + hw->phy.id = identifier;
1730 +
1731 + status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1732 + &comp_codes_10g);
1733 +
1734 + if (status != IXGBE_SUCCESS)
1735 + goto err_read_i2c_eeprom;
1736 +
1737 + status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1738 + &comp_codes_1g);
1739 +
1740 + if (status != IXGBE_SUCCESS)
1741 + goto err_read_i2c_eeprom;
1742 +
1743 + if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1744 + hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1745 + if (hw->bus.lan_id == 0)
1746 + hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1747 + else
1748 + hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1749 + } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1750 + IXGBE_SFF_10GBASELR_CAPABLE)) {
1751 + if (hw->bus.lan_id == 0)
1752 + hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1753 + else
1754 + hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1755 + } else {
1756 + if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1757 + active_cable = TRUE;
1758 +
1759 + if (!active_cable) {
1760 + /* check for active DA cables that pre-date
1761 + * SFF-8436 v3.6 */
1762 + hw->phy.ops.read_i2c_eeprom(hw,
1763 + IXGBE_SFF_QSFP_CONNECTOR,
1764 + &connector);
1765 +
1766 + hw->phy.ops.read_i2c_eeprom(hw,
1767 + IXGBE_SFF_QSFP_CABLE_LENGTH,
1768 + &cable_length);
1769 +
1770 + hw->phy.ops.read_i2c_eeprom(hw,
1771 + IXGBE_SFF_QSFP_DEVICE_TECH,
1772 + &device_tech);
1773 +
1774 + if ((connector ==
1775 + IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1776 + (cable_length > 0) &&
1777 + ((device_tech >> 4) ==
1778 + IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1779 + active_cable = TRUE;
1780 + }
1781 +
1782 + if (active_cable) {
1783 + hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1784 + if (hw->bus.lan_id == 0)
1785 + hw->phy.sfp_type =
1786 + ixgbe_sfp_type_da_act_lmt_core0;
1787 + else
1788 + hw->phy.sfp_type =
1789 + ixgbe_sfp_type_da_act_lmt_core1;
1790 + } else {
1791 + /* unsupported module type */
1792 + hw->phy.type = ixgbe_phy_sfp_unsupported;
1793 + status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1794 + goto out;
1795 + }
1796 + }
1797 +
1798 + if (hw->phy.sfp_type != stored_sfp_type)
1799 + hw->phy.sfp_setup_needed = TRUE;
1800 +
1801 + /* Determine if the QSFP+ PHY is dual speed or not. */
1802 + hw->phy.multispeed_fiber = FALSE;
1803 + if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1804 + (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1805 + ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1806 + (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1807 + hw->phy.multispeed_fiber = TRUE;
1808 +
1809 + /* Determine PHY vendor for optical modules */
1810 + if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1811 + IXGBE_SFF_10GBASELR_CAPABLE)) {
1812 + status = hw->phy.ops.read_i2c_eeprom(hw,
1813 + IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1814 + &oui_bytes[0]);
1815 +
1816 + if (status != IXGBE_SUCCESS)
1817 + goto err_read_i2c_eeprom;
1818 +
1819 + status = hw->phy.ops.read_i2c_eeprom(hw,
1820 + IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1821 + &oui_bytes[1]);
1822 +
1823 + if (status != IXGBE_SUCCESS)
1824 + goto err_read_i2c_eeprom;
1825 +
1826 + status = hw->phy.ops.read_i2c_eeprom(hw,
1827 + IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1828 + &oui_bytes[2]);
1829 +
1830 + if (status != IXGBE_SUCCESS)
1831 + goto err_read_i2c_eeprom;
1832 +
1833 + vendor_oui =
1834 + ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1835 + (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1836 + (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1837 +
1838 + if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1839 + hw->phy.type = ixgbe_phy_qsfp_intel;
1840 + else
1841 + hw->phy.type = ixgbe_phy_qsfp_unknown;
1842 +
1843 + ixgbe_get_device_caps(hw, &enforce_sfp);
1844 + if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1845 + /* Make sure we're a supported PHY type */
1846 + if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1847 + status = IXGBE_SUCCESS;
1848 + } else {
1849 + if (hw->allow_unsupported_sfp == TRUE) {
1850 + EWARN(hw, "WARNING: Intel (R) Network "
1851 + "Connections are quality tested "
1852 + "using Intel (R) Ethernet Optics."
1853 + " Using untested modules is not "
1854 + "supported and may cause unstable"
1855 + " operation or damage to the "
1856 + "module or the adapter. Intel "
1857 + "Corporation is not responsible "
1858 + "for any harm caused by using "
1859 + "untested modules.\n", status);
1860 + status = IXGBE_SUCCESS;
1861 + } else {
1862 + DEBUGOUT("QSFP module not supported\n");
1863 + hw->phy.type =
1864 + ixgbe_phy_sfp_unsupported;
1865 + status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1866 + }
1867 + }
1868 + } else {
1869 + status = IXGBE_SUCCESS;
1870 + }
1871 + }
1872 +
1873 +out:
1874 + return status;
1875 +
1876 +err_read_i2c_eeprom:
1877 + hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1878 + hw->phy.id = 0;
1879 + hw->phy.type = ixgbe_phy_unknown;
1880 +
1881 + return IXGBE_ERR_SFP_NOT_PRESENT;
1882 +}
1883 +
1884 +
1885 +/**
1255 1886 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1256 1887 * @hw: pointer to hardware structure
1257 1888 * @list_offset: offset to the SFP ID list
1258 1889 * @data_offset: offset to the SFP data block
1259 1890 *
1260 1891 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1261 1892 * so it returns the offsets to the phy init sequence block.
1262 1893 **/
1263 1894 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1264 1895 u16 *list_offset,
1265 1896 u16 *data_offset)
1266 1897 {
1267 1898 u16 sfp_id;
1268 1899 u16 sfp_type = hw->phy.sfp_type;
1269 1900
1270 1901 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1271 1902
1272 1903 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1273 1904 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1274 1905
1275 1906 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1276 1907 return IXGBE_ERR_SFP_NOT_PRESENT;
1277 1908
1278 1909 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1279 1910 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1280 1911 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1281 1912
1282 1913 /*
1283 1914 * Limiting active cables and 1G Phys must be initialized as
1284 1915 * SR modules
1285 1916 */
1286 1917 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1287 1918 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
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1288 1919 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1289 1920 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1290 1921 sfp_type = ixgbe_sfp_type_srlr_core0;
1291 1922 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1292 1923 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1293 1924 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1294 1925 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1295 1926 sfp_type = ixgbe_sfp_type_srlr_core1;
1296 1927
1297 1928 /* Read offset to PHY init contents */
1298 - hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1929 + if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1930 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1931 + "eeprom read at offset %d failed",
1932 + IXGBE_PHY_INIT_OFFSET_NL);
1933 + return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1934 + }
1299 1935
1300 1936 if ((!*list_offset) || (*list_offset == 0xFFFF))
1301 1937 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1302 1938
1303 1939 /* Shift offset to first ID word */
1304 1940 (*list_offset)++;
1305 1941
1306 1942 /*
1307 1943 * Find the matching SFP ID in the EEPROM
1308 1944 * and program the init sequence
1309 1945 */
1310 - hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1946 + if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1947 + goto err_phy;
1311 1948
1312 1949 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1313 1950 if (sfp_id == sfp_type) {
1314 1951 (*list_offset)++;
1315 - hw->eeprom.ops.read(hw, *list_offset, data_offset);
1952 + if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1953 + goto err_phy;
1316 1954 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1317 1955 DEBUGOUT("SFP+ module not supported\n");
1318 1956 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1319 1957 } else {
1320 1958 break;
1321 1959 }
1322 1960 } else {
1323 1961 (*list_offset) += 2;
1324 1962 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1325 - return IXGBE_ERR_PHY;
1963 + goto err_phy;
1326 1964 }
1327 1965 }
1328 1966
1329 1967 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1330 1968 DEBUGOUT("No matching SFP+ module found\n");
1331 1969 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1332 1970 }
1333 1971
1334 1972 return IXGBE_SUCCESS;
1973 +
1974 +err_phy:
1975 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1976 + "eeprom read at offset %d failed", *list_offset);
1977 + return IXGBE_ERR_PHY;
1335 1978 }
1336 1979
1337 1980 /**
1338 1981 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1339 1982 * @hw: pointer to hardware structure
1340 1983 * @byte_offset: EEPROM byte offset to read
1341 1984 * @eeprom_data: value read
1342 1985 *
1343 1986 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1344 1987 **/
1345 1988 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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1346 1989 u8 *eeprom_data)
1347 1990 {
1348 1991 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1349 1992
1350 1993 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1351 1994 IXGBE_I2C_EEPROM_DEV_ADDR,
1352 1995 eeprom_data);
1353 1996 }
1354 1997
1355 1998 /**
1999 + * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2000 + * @hw: pointer to hardware structure
2001 + * @byte_offset: byte offset at address 0xA2
2002 + * @eeprom_data: value read
2003 + *
2004 + * Performs byte read operation to SFP module's SFF-8472 data over I2C
2005 + **/
2006 +static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2007 + u8 *sff8472_data)
2008 +{
2009 + return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2010 + IXGBE_I2C_EEPROM_DEV_ADDR2,
2011 + sff8472_data);
2012 +}
2013 +
2014 +/**
1356 2015 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1357 2016 * @hw: pointer to hardware structure
1358 2017 * @byte_offset: EEPROM byte offset to write
1359 2018 * @eeprom_data: value to write
1360 2019 *
1361 2020 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1362 2021 **/
1363 2022 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1364 2023 u8 eeprom_data)
1365 2024 {
1366 2025 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1367 2026
1368 2027 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1369 2028 IXGBE_I2C_EEPROM_DEV_ADDR,
1370 2029 eeprom_data);
1371 2030 }
1372 2031
1373 2032 /**
1374 - * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2033 + * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
2034 + * @hw: pointer to hardware structure
2035 + * @offset: eeprom offset to be read
2036 + * @addr: I2C address to be read
2037 + */
2038 +static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2039 +{
2040 + if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2041 + offset == IXGBE_SFF_IDENTIFIER &&
2042 + hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2043 + return TRUE;
2044 + return FALSE;
2045 +}
2046 +
2047 +/**
2048 + * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1375 2049 * @hw: pointer to hardware structure
1376 2050 * @byte_offset: byte offset to read
1377 2051 * @data: value read
2052 + * @lock: TRUE if to take and release semaphore
1378 2053 *
1379 2054 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1380 2055 * a specified device address.
1381 2056 **/
1382 -s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1383 - u8 dev_addr, u8 *data)
2057 +static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2058 + u8 dev_addr, u8 *data, bool lock)
1384 2059 {
1385 - s32 status = IXGBE_SUCCESS;
2060 + s32 status;
1386 2061 u32 max_retry = 10;
1387 2062 u32 retry = 0;
1388 - u16 swfw_mask = 0;
2063 + u32 swfw_mask = hw->phy.phy_semaphore_mask;
1389 2064 bool nack = 1;
1390 2065 *data = 0;
1391 2066
1392 2067 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1393 2068
1394 - if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1395 - swfw_mask = IXGBE_GSSR_PHY1_SM;
1396 - else
1397 - swfw_mask = IXGBE_GSSR_PHY0_SM;
2069 + if (hw->mac.type >= ixgbe_mac_X550)
2070 + max_retry = 3;
2071 + if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2072 + max_retry = IXGBE_SFP_DETECT_RETRIES;
1398 2073
1399 2074 do {
1400 - if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1401 - != IXGBE_SUCCESS) {
1402 - status = IXGBE_ERR_SWFW_SYNC;
1403 - goto read_byte_out;
1404 - }
2075 + if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2076 + return IXGBE_ERR_SWFW_SYNC;
1405 2077
1406 2078 ixgbe_i2c_start(hw);
1407 2079
1408 2080 /* Device Address and write indication */
1409 2081 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1410 2082 if (status != IXGBE_SUCCESS)
1411 2083 goto fail;
1412 2084
1413 2085 status = ixgbe_get_i2c_ack(hw);
1414 2086 if (status != IXGBE_SUCCESS)
1415 2087 goto fail;
1416 2088
1417 2089 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1418 2090 if (status != IXGBE_SUCCESS)
1419 2091 goto fail;
1420 2092
1421 2093 status = ixgbe_get_i2c_ack(hw);
1422 2094 if (status != IXGBE_SUCCESS)
1423 2095 goto fail;
1424 2096
1425 2097 ixgbe_i2c_start(hw);
1426 2098
1427 2099 /* Device Address and read indication */
1428 2100 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1429 2101 if (status != IXGBE_SUCCESS)
1430 2102 goto fail;
1431 2103
1432 2104 status = ixgbe_get_i2c_ack(hw);
1433 2105 if (status != IXGBE_SUCCESS)
1434 2106 goto fail;
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1435 2107
1436 2108 status = ixgbe_clock_in_i2c_byte(hw, data);
1437 2109 if (status != IXGBE_SUCCESS)
1438 2110 goto fail;
1439 2111
1440 2112 status = ixgbe_clock_out_i2c_bit(hw, nack);
1441 2113 if (status != IXGBE_SUCCESS)
1442 2114 goto fail;
1443 2115
1444 2116 ixgbe_i2c_stop(hw);
1445 - break;
2117 + if (lock)
2118 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2119 + return IXGBE_SUCCESS;
1446 2120
1447 2121 fail:
1448 - hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1449 - msec_delay(100);
1450 2122 ixgbe_i2c_bus_clear(hw);
2123 + if (lock) {
2124 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2125 + msec_delay(100);
2126 + }
1451 2127 retry++;
1452 2128 if (retry < max_retry)
1453 2129 DEBUGOUT("I2C byte read error - Retrying.\n");
1454 2130 else
1455 2131 DEBUGOUT("I2C byte read error.\n");
1456 2132
1457 2133 } while (retry < max_retry);
1458 2134
1459 - hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1460 -
1461 -read_byte_out:
1462 2135 return status;
1463 2136 }
1464 2137
1465 2138 /**
1466 - * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2139 + * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1467 2140 * @hw: pointer to hardware structure
2141 + * @byte_offset: byte offset to read
2142 + * @data: value read
2143 + *
2144 + * Performs byte read operation to SFP module's EEPROM over I2C interface at
2145 + * a specified device address.
2146 + **/
2147 +s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2148 + u8 dev_addr, u8 *data)
2149 +{
2150 + return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2151 + data, TRUE);
2152 +}
2153 +
2154 +/**
2155 + * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2156 + * @hw: pointer to hardware structure
2157 + * @byte_offset: byte offset to read
2158 + * @data: value read
2159 + *
2160 + * Performs byte read operation to SFP module's EEPROM over I2C interface at
2161 + * a specified device address.
2162 + **/
2163 +s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2164 + u8 dev_addr, u8 *data)
2165 +{
2166 + return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2167 + data, FALSE);
2168 +}
2169 +
2170 +/**
2171 + * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2172 + * @hw: pointer to hardware structure
1468 2173 * @byte_offset: byte offset to write
1469 2174 * @data: value to write
2175 + * @lock: TRUE if to take and release semaphore
1470 2176 *
1471 2177 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1472 2178 * a specified device address.
1473 2179 **/
1474 -s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1475 - u8 dev_addr, u8 data)
2180 +static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2181 + u8 dev_addr, u8 data, bool lock)
1476 2182 {
1477 - s32 status = IXGBE_SUCCESS;
2183 + s32 status;
1478 2184 u32 max_retry = 1;
1479 2185 u32 retry = 0;
1480 - u16 swfw_mask = 0;
2186 + u32 swfw_mask = hw->phy.phy_semaphore_mask;
1481 2187
1482 2188 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1483 2189
1484 - if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1485 - swfw_mask = IXGBE_GSSR_PHY1_SM;
1486 - else
1487 - swfw_mask = IXGBE_GSSR_PHY0_SM;
2190 + if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2191 + IXGBE_SUCCESS)
2192 + return IXGBE_ERR_SWFW_SYNC;
1488 2193
1489 - if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1490 - status = IXGBE_ERR_SWFW_SYNC;
1491 - goto write_byte_out;
1492 - }
1493 -
1494 2194 do {
1495 2195 ixgbe_i2c_start(hw);
1496 2196
1497 2197 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1498 2198 if (status != IXGBE_SUCCESS)
1499 2199 goto fail;
1500 2200
1501 2201 status = ixgbe_get_i2c_ack(hw);
1502 2202 if (status != IXGBE_SUCCESS)
1503 2203 goto fail;
1504 2204
1505 2205 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1506 2206 if (status != IXGBE_SUCCESS)
1507 2207 goto fail;
1508 2208
1509 2209 status = ixgbe_get_i2c_ack(hw);
1510 2210 if (status != IXGBE_SUCCESS)
1511 2211 goto fail;
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1512 2212
1513 2213 status = ixgbe_clock_out_i2c_byte(hw, data);
1514 2214 if (status != IXGBE_SUCCESS)
1515 2215 goto fail;
1516 2216
1517 2217 status = ixgbe_get_i2c_ack(hw);
1518 2218 if (status != IXGBE_SUCCESS)
1519 2219 goto fail;
1520 2220
1521 2221 ixgbe_i2c_stop(hw);
1522 - break;
2222 + if (lock)
2223 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2224 + return IXGBE_SUCCESS;
1523 2225
1524 2226 fail:
1525 2227 ixgbe_i2c_bus_clear(hw);
1526 2228 retry++;
1527 2229 if (retry < max_retry)
1528 2230 DEBUGOUT("I2C byte write error - Retrying.\n");
1529 2231 else
1530 2232 DEBUGOUT("I2C byte write error.\n");
1531 2233 } while (retry < max_retry);
1532 2234
1533 - hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2235 + if (lock)
2236 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1534 2237
1535 -write_byte_out:
1536 2238 return status;
1537 2239 }
1538 2240
1539 2241 /**
2242 + * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2243 + * @hw: pointer to hardware structure
2244 + * @byte_offset: byte offset to write
2245 + * @data: value to write
2246 + *
2247 + * Performs byte write operation to SFP module's EEPROM over I2C interface at
2248 + * a specified device address.
2249 + **/
2250 +s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2251 + u8 dev_addr, u8 data)
2252 +{
2253 + return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2254 + data, TRUE);
2255 +}
2256 +
2257 +/**
2258 + * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2259 + * @hw: pointer to hardware structure
2260 + * @byte_offset: byte offset to write
2261 + * @data: value to write
2262 + *
2263 + * Performs byte write operation to SFP module's EEPROM over I2C interface at
2264 + * a specified device address.
2265 + **/
2266 +s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2267 + u8 dev_addr, u8 data)
2268 +{
2269 + return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2270 + data, FALSE);
2271 +}
2272 +
2273 +/**
1540 2274 * ixgbe_i2c_start - Sets I2C start condition
1541 2275 * @hw: pointer to hardware structure
1542 2276 *
1543 2277 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2278 + * Set bit-bang mode on X550 hardware.
1544 2279 **/
1545 2280 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1546 2281 {
1547 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2282 + u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1548 2283
1549 2284 DEBUGFUNC("ixgbe_i2c_start");
1550 2285
2286 + i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2287 +
1551 2288 /* Start condition must begin with data and clock high */
1552 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
2289 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1553 2290 ixgbe_raise_i2c_clk(hw, &i2cctl);
1554 2291
1555 2292 /* Setup time for start condition (4.7us) */
1556 2293 usec_delay(IXGBE_I2C_T_SU_STA);
1557 2294
1558 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
2295 + ixgbe_set_i2c_data(hw, &i2cctl, 0);
1559 2296
1560 2297 /* Hold time for start condition (4us) */
1561 2298 usec_delay(IXGBE_I2C_T_HD_STA);
1562 2299
1563 2300 ixgbe_lower_i2c_clk(hw, &i2cctl);
1564 2301
1565 2302 /* Minimum low period of clock is 4.7 us */
1566 2303 usec_delay(IXGBE_I2C_T_LOW);
1567 2304
1568 2305 }
1569 2306
1570 2307 /**
1571 2308 * ixgbe_i2c_stop - Sets I2C stop condition
1572 2309 * @hw: pointer to hardware structure
1573 2310 *
1574 2311 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2312 + * Disables bit-bang mode and negates data output enable on X550
2313 + * hardware.
1575 2314 **/
1576 2315 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1577 2316 {
1578 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2317 + u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2318 + u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2319 + u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2320 + u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
1579 2321
1580 2322 DEBUGFUNC("ixgbe_i2c_stop");
1581 2323
1582 2324 /* Stop condition must begin with data low and clock high */
1583 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
2325 + ixgbe_set_i2c_data(hw, &i2cctl, 0);
1584 2326 ixgbe_raise_i2c_clk(hw, &i2cctl);
1585 2327
1586 2328 /* Setup time for stop condition (4us) */
1587 2329 usec_delay(IXGBE_I2C_T_SU_STO);
1588 2330
1589 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
2331 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1590 2332
1591 2333 /* bus free time between stop and start (4.7us)*/
1592 2334 usec_delay(IXGBE_I2C_T_BUF);
2335 +
2336 + if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2337 + i2cctl &= ~bb_en_bit;
2338 + i2cctl |= data_oe_bit | clk_oe_bit;
2339 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2340 + IXGBE_WRITE_FLUSH(hw);
2341 + }
1593 2342 }
1594 2343
1595 2344 /**
1596 2345 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1597 2346 * @hw: pointer to hardware structure
1598 2347 * @data: data byte to clock in
1599 2348 *
1600 2349 * Clocks in one byte data via I2C data/clock
1601 2350 **/
1602 2351 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1603 2352 {
1604 - s32 i, status = IXGBE_SUCCESS;
2353 + s32 i;
1605 2354 bool bit = 0;
1606 2355
1607 2356 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1608 2357
2358 + *data = 0;
1609 2359 for (i = 7; i >= 0; i--) {
1610 - status = ixgbe_clock_in_i2c_bit(hw, &bit);
1611 - if (status != IXGBE_SUCCESS)
1612 - break;
2360 + ixgbe_clock_in_i2c_bit(hw, &bit);
1613 2361 *data |= bit << i;
1614 2362 }
1615 2363
1616 - return status;
2364 + return IXGBE_SUCCESS;
1617 2365 }
1618 2366
1619 2367 /**
1620 2368 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1621 2369 * @hw: pointer to hardware structure
1622 2370 * @data: data byte clocked out
1623 2371 *
1624 2372 * Clocks out one byte data via I2C data/clock
1625 2373 **/
1626 2374 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1627 2375 {
1628 2376 s32 status = IXGBE_SUCCESS;
1629 2377 s32 i;
1630 2378 u32 i2cctl;
1631 - bool bit = 0;
2379 + bool bit;
1632 2380
1633 2381 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1634 2382
1635 2383 for (i = 7; i >= 0; i--) {
1636 2384 bit = (data >> i) & 0x1;
1637 2385 status = ixgbe_clock_out_i2c_bit(hw, bit);
1638 2386
1639 2387 if (status != IXGBE_SUCCESS)
1640 2388 break;
1641 2389 }
1642 2390
1643 2391 /* Release SDA line (set high) */
1644 - i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1645 - i2cctl |= IXGBE_I2C_DATA_OUT;
1646 - IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
2392 + i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2393 + i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2394 + i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2395 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
1647 2396 IXGBE_WRITE_FLUSH(hw);
1648 2397
1649 2398 return status;
1650 2399 }
1651 2400
1652 2401 /**
1653 2402 * ixgbe_get_i2c_ack - Polls for I2C ACK
1654 2403 * @hw: pointer to hardware structure
1655 2404 *
1656 2405 * Clocks in/out one bit via I2C data/clock
1657 2406 **/
1658 2407 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1659 2408 {
2409 + u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
1660 2410 s32 status = IXGBE_SUCCESS;
1661 2411 u32 i = 0;
1662 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2412 + u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1663 2413 u32 timeout = 10;
1664 2414 bool ack = 1;
1665 2415
1666 2416 DEBUGFUNC("ixgbe_get_i2c_ack");
1667 2417
2418 + if (data_oe_bit) {
2419 + i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2420 + i2cctl |= data_oe_bit;
2421 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2422 + IXGBE_WRITE_FLUSH(hw);
2423 + }
1668 2424 ixgbe_raise_i2c_clk(hw, &i2cctl);
1669 2425
1670 -
1671 2426 /* Minimum high period of clock is 4us */
1672 2427 usec_delay(IXGBE_I2C_T_HIGH);
1673 2428
1674 2429 /* Poll for ACK. Note that ACK in I2C spec is
1675 2430 * transition from 1 to 0 */
1676 2431 for (i = 0; i < timeout; i++) {
1677 - i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1678 - ack = ixgbe_get_i2c_data(&i2cctl);
2432 + i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2433 + ack = ixgbe_get_i2c_data(hw, &i2cctl);
1679 2434
1680 2435 usec_delay(1);
1681 - if (ack == 0)
2436 + if (!ack)
1682 2437 break;
1683 2438 }
1684 2439
1685 - if (ack == 1) {
2440 + if (ack) {
1686 2441 DEBUGOUT("I2C ack was not received.\n");
1687 2442 status = IXGBE_ERR_I2C;
1688 2443 }
1689 2444
1690 2445 ixgbe_lower_i2c_clk(hw, &i2cctl);
1691 2446
1692 2447 /* Minimum low period of clock is 4.7 us */
1693 2448 usec_delay(IXGBE_I2C_T_LOW);
1694 2449
1695 2450 return status;
1696 2451 }
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1697 2452
1698 2453 /**
1699 2454 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1700 2455 * @hw: pointer to hardware structure
1701 2456 * @data: read data value
1702 2457 *
1703 2458 * Clocks in one bit via I2C data/clock
1704 2459 **/
1705 2460 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1706 2461 {
1707 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2462 + u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2463 + u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
1708 2464
1709 2465 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1710 2466
2467 + if (data_oe_bit) {
2468 + i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2469 + i2cctl |= data_oe_bit;
2470 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2471 + IXGBE_WRITE_FLUSH(hw);
2472 + }
1711 2473 ixgbe_raise_i2c_clk(hw, &i2cctl);
1712 2474
1713 2475 /* Minimum high period of clock is 4us */
1714 2476 usec_delay(IXGBE_I2C_T_HIGH);
1715 2477
1716 - i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1717 - *data = ixgbe_get_i2c_data(&i2cctl);
2478 + i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2479 + *data = ixgbe_get_i2c_data(hw, &i2cctl);
1718 2480
1719 2481 ixgbe_lower_i2c_clk(hw, &i2cctl);
1720 2482
1721 2483 /* Minimum low period of clock is 4.7 us */
1722 2484 usec_delay(IXGBE_I2C_T_LOW);
1723 2485
1724 2486 return IXGBE_SUCCESS;
1725 2487 }
1726 2488
1727 2489 /**
1728 2490 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1729 2491 * @hw: pointer to hardware structure
1730 2492 * @data: data value to write
1731 2493 *
1732 2494 * Clocks out one bit via I2C data/clock
1733 2495 **/
1734 2496 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1735 2497 {
1736 2498 s32 status;
1737 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2499 + u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1738 2500
1739 2501 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1740 2502
1741 2503 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1742 2504 if (status == IXGBE_SUCCESS) {
1743 2505 ixgbe_raise_i2c_clk(hw, &i2cctl);
1744 2506
1745 2507 /* Minimum high period of clock is 4us */
1746 2508 usec_delay(IXGBE_I2C_T_HIGH);
1747 2509
1748 2510 ixgbe_lower_i2c_clk(hw, &i2cctl);
1749 2511
1750 2512 /* Minimum low period of clock is 4.7 us.
1751 2513 * This also takes care of the data hold time.
1752 2514 */
1753 2515 usec_delay(IXGBE_I2C_T_LOW);
1754 2516 } else {
1755 2517 status = IXGBE_ERR_I2C;
1756 - DEBUGOUT1("I2C data was not set to %X\n", data);
2518 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2519 + "I2C data was not set to %X\n", data);
1757 2520 }
1758 2521
1759 2522 return status;
1760 2523 }
2524 +
1761 2525 /**
1762 2526 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1763 2527 * @hw: pointer to hardware structure
1764 2528 * @i2cctl: Current value of I2CCTL register
1765 2529 *
1766 2530 * Raises the I2C clock line '0'->'1'
2531 + * Negates the I2C clock output enable on X550 hardware.
1767 2532 **/
1768 2533 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1769 2534 {
2535 + u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
1770 2536 u32 i = 0;
1771 2537 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1772 2538 u32 i2cctl_r = 0;
1773 2539
1774 2540 DEBUGFUNC("ixgbe_raise_i2c_clk");
1775 2541
2542 + if (clk_oe_bit) {
2543 + *i2cctl |= clk_oe_bit;
2544 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2545 + }
2546 +
1776 2547 for (i = 0; i < timeout; i++) {
1777 - *i2cctl |= IXGBE_I2C_CLK_OUT;
2548 + *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
1778 2549
1779 - IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2550 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1780 2551 IXGBE_WRITE_FLUSH(hw);
1781 2552 /* SCL rise time (1000ns) */
1782 2553 usec_delay(IXGBE_I2C_T_RISE);
1783 2554
1784 - i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1785 - if (i2cctl_r & IXGBE_I2C_CLK_IN)
2555 + i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2556 + if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
1786 2557 break;
1787 2558 }
1788 2559 }
1789 2560
1790 2561 /**
1791 2562 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1792 2563 * @hw: pointer to hardware structure
1793 2564 * @i2cctl: Current value of I2CCTL register
1794 2565 *
1795 2566 * Lowers the I2C clock line '1'->'0'
2567 + * Asserts the I2C clock output enable on X550 hardware.
1796 2568 **/
1797 2569 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1798 2570 {
1799 -
1800 2571 DEBUGFUNC("ixgbe_lower_i2c_clk");
1801 2572
1802 - *i2cctl &= ~IXGBE_I2C_CLK_OUT;
2573 + *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2574 + *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
1803 2575
1804 - IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2576 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1805 2577 IXGBE_WRITE_FLUSH(hw);
1806 2578
1807 2579 /* SCL fall time (300ns) */
1808 2580 usec_delay(IXGBE_I2C_T_FALL);
1809 2581 }
1810 2582
1811 2583 /**
1812 2584 * ixgbe_set_i2c_data - Sets the I2C data bit
1813 2585 * @hw: pointer to hardware structure
1814 2586 * @i2cctl: Current value of I2CCTL register
1815 2587 * @data: I2C data value (0 or 1) to set
1816 2588 *
1817 2589 * Sets the I2C data bit
2590 + * Asserts the I2C data output enable on X550 hardware.
1818 2591 **/
1819 2592 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1820 2593 {
2594 + u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
1821 2595 s32 status = IXGBE_SUCCESS;
1822 2596
1823 2597 DEBUGFUNC("ixgbe_set_i2c_data");
1824 2598
1825 2599 if (data)
1826 - *i2cctl |= IXGBE_I2C_DATA_OUT;
2600 + *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1827 2601 else
1828 - *i2cctl &= ~IXGBE_I2C_DATA_OUT;
2602 + *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2603 + *i2cctl &= ~data_oe_bit;
1829 2604
1830 - IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2605 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1831 2606 IXGBE_WRITE_FLUSH(hw);
1832 2607
1833 2608 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1834 2609 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1835 2610
2611 + if (!data) /* Can't verify data in this case */
2612 + return IXGBE_SUCCESS;
2613 + if (data_oe_bit) {
2614 + *i2cctl |= data_oe_bit;
2615 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2616 + IXGBE_WRITE_FLUSH(hw);
2617 + }
2618 +
1836 2619 /* Verify data was set correctly */
1837 - *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1838 - if (data != ixgbe_get_i2c_data(i2cctl)) {
2620 + *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2621 + if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
1839 2622 status = IXGBE_ERR_I2C;
1840 - DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
2623 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2624 + "Error - I2C data was not set to %X.\n",
2625 + data);
1841 2626 }
1842 2627
1843 2628 return status;
1844 2629 }
1845 2630
1846 2631 /**
1847 2632 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1848 2633 * @hw: pointer to hardware structure
1849 2634 * @i2cctl: Current value of I2CCTL register
1850 2635 *
1851 2636 * Returns the I2C data bit value
2637 + * Negates the I2C data output enable on X550 hardware.
1852 2638 **/
1853 -static bool ixgbe_get_i2c_data(u32 *i2cctl)
2639 +static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
1854 2640 {
2641 + u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
1855 2642 bool data;
1856 2643
1857 2644 DEBUGFUNC("ixgbe_get_i2c_data");
1858 2645
1859 - if (*i2cctl & IXGBE_I2C_DATA_IN)
2646 + if (data_oe_bit) {
2647 + *i2cctl |= data_oe_bit;
2648 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2649 + IXGBE_WRITE_FLUSH(hw);
2650 + usec_delay(IXGBE_I2C_T_FALL);
2651 + }
2652 +
2653 + if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
1860 2654 data = 1;
1861 2655 else
1862 2656 data = 0;
1863 2657
1864 2658 return data;
1865 2659 }
1866 2660
1867 2661 /**
1868 2662 * ixgbe_i2c_bus_clear - Clears the I2C bus
1869 2663 * @hw: pointer to hardware structure
1870 2664 *
1871 2665 * Clears the I2C bus by sending nine clock pulses.
1872 2666 * Used when data line is stuck low.
1873 2667 **/
1874 2668 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1875 2669 {
1876 - u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2670 + u32 i2cctl;
1877 2671 u32 i;
1878 2672
1879 2673 DEBUGFUNC("ixgbe_i2c_bus_clear");
1880 2674
1881 2675 ixgbe_i2c_start(hw);
2676 + i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1882 2677
1883 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
2678 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1884 2679
1885 2680 for (i = 0; i < 9; i++) {
1886 2681 ixgbe_raise_i2c_clk(hw, &i2cctl);
1887 2682
1888 2683 /* Min high period of clock is 4us */
1889 2684 usec_delay(IXGBE_I2C_T_HIGH);
1890 2685
1891 2686 ixgbe_lower_i2c_clk(hw, &i2cctl);
1892 2687
1893 2688 /* Min low period of clock is 4.7us*/
1894 2689 usec_delay(IXGBE_I2C_T_LOW);
1895 2690 }
1896 2691
1897 2692 ixgbe_i2c_start(hw);
1898 2693
1899 2694 /* Put the i2c bus back to default state */
1900 2695 ixgbe_i2c_stop(hw);
1901 2696 }
1902 2697
1903 2698 /**
1904 2699 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1905 2700 * @hw: pointer to hardware structure
1906 2701 *
1907 2702 * Checks if the LASI temp alarm status was triggered due to overtemp
1908 2703 **/
1909 2704 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1910 2705 {
1911 2706 s32 status = IXGBE_SUCCESS;
1912 2707 u16 phy_data = 0;
1913 2708
1914 2709 DEBUGFUNC("ixgbe_tn_check_overtemp");
1915 2710
1916 2711 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
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1917 2712 goto out;
1918 2713
1919 2714 /* Check that the LASI temp alarm status was triggered */
1920 2715 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1921 2716 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1922 2717
1923 2718 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1924 2719 goto out;
1925 2720
1926 2721 status = IXGBE_ERR_OVERTEMP;
2722 + ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
1927 2723 out:
1928 2724 return status;
1929 2725 }
2726 +
2727 +/**
2728 + * ixgbe_set_copper_phy_power - Control power for copper phy
2729 + * @hw: pointer to hardware structure
2730 + * @on: TRUE for on, FALSE for off
2731 + */
2732 +s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2733 +{
2734 + u32 status;
2735 + u16 reg;
2736 +
2737 + if (!on && ixgbe_mng_present(hw))
2738 + return 0;
2739 +
2740 + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2741 + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2742 + ®);
2743 + if (status)
2744 + return status;
2745 +
2746 + if (on) {
2747 + reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2748 + } else {
2749 + if (ixgbe_check_reset_blocked(hw))
2750 + return 0;
2751 + reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2752 + }
2753 +
2754 + status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2755 + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2756 + reg);
2757 + return status;
2758 +}
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