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6064 ixgbe needs X550 support

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          --- old/usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
          +++ new/usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
   1    1  /******************************************************************************
   2    2  
   3      -  Copyright (c) 2001-2012, Intel Corporation 
        3 +  Copyright (c) 2001-2015, Intel Corporation 
   4    4    All rights reserved.
   5    5    
   6    6    Redistribution and use in source and binary forms, with or without 
   7    7    modification, are permitted provided that the following conditions are met:
   8    8    
   9    9     1. Redistributions of source code must retain the above copyright notice, 
  10   10        this list of conditions and the following disclaimer.
  11   11    
  12   12     2. Redistributions in binary form must reproduce the above copyright 
  13   13        notice, this list of conditions and the following disclaimer in the 
↓ open down ↓ 9 lines elided ↑ open up ↑
  23   23    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   24    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   25    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   26    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   27    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   28    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   29    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   30    POSSIBILITY OF SUCH DAMAGE.
  31   31  
  32   32  ******************************************************************************/
  33      -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
       33 +/*$FreeBSD$*/
  34   34  
  35   35  #include "ixgbe_common.h"
  36   36  #include "ixgbe_phy.h"
       37 +#include "ixgbe_dcb.h"
       38 +#include "ixgbe_dcb_82599.h"
  37   39  #include "ixgbe_api.h"
  38   40  
  39   41  static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
  40   42  static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
  41   43  static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
  42   44  static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
  43   45  static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
  44   46  static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
  45   47                                          u16 count);
  46   48  static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
↓ open down ↓ 14 lines elided ↑ open up ↑
  61   63  /**
  62   64   *  ixgbe_init_ops_generic - Inits function ptrs
  63   65   *  @hw: pointer to the hardware structure
  64   66   *
  65   67   *  Initialize the function pointers.
  66   68   **/
  67   69  s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
  68   70  {
  69   71          struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  70   72          struct ixgbe_mac_info *mac = &hw->mac;
  71      -        u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
       73 +        u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
  72   74  
  73   75          DEBUGFUNC("ixgbe_init_ops_generic");
  74   76  
  75   77          /* EEPROM */
  76      -        eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
       78 +        eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
  77   79          /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
  78   80          if (eec & IXGBE_EEC_PRES) {
  79      -                eeprom->ops.read = &ixgbe_read_eerd_generic;
  80      -                eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
       81 +                eeprom->ops.read = ixgbe_read_eerd_generic;
       82 +                eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
  81   83          } else {
  82      -                eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
       84 +                eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
  83   85                  eeprom->ops.read_buffer =
  84      -                                 &ixgbe_read_eeprom_buffer_bit_bang_generic;
       86 +                                 ixgbe_read_eeprom_buffer_bit_bang_generic;
  85   87          }
  86      -        eeprom->ops.write = &ixgbe_write_eeprom_generic;
  87      -        eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
       88 +        eeprom->ops.write = ixgbe_write_eeprom_generic;
       89 +        eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
  88   90          eeprom->ops.validate_checksum =
  89      -                                      &ixgbe_validate_eeprom_checksum_generic;
  90      -        eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
  91      -        eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
       91 +                                      ixgbe_validate_eeprom_checksum_generic;
       92 +        eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
       93 +        eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
  92   94  
  93   95          /* MAC */
  94      -        mac->ops.init_hw = &ixgbe_init_hw_generic;
       96 +        mac->ops.init_hw = ixgbe_init_hw_generic;
  95   97          mac->ops.reset_hw = NULL;
  96      -        mac->ops.start_hw = &ixgbe_start_hw_generic;
  97      -        mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
       98 +        mac->ops.start_hw = ixgbe_start_hw_generic;
       99 +        mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
  98  100          mac->ops.get_media_type = NULL;
  99  101          mac->ops.get_supported_physical_layer = NULL;
 100      -        mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
 101      -        mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
 102      -        mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
 103      -        mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
 104      -        mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
 105      -        mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
 106      -        mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
      102 +        mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
      103 +        mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
      104 +        mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
      105 +        mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
      106 +        mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
      107 +        mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
      108 +        mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
      109 +        mac->ops.prot_autoc_read = prot_autoc_read_generic;
      110 +        mac->ops.prot_autoc_write = prot_autoc_write_generic;
 107  111  
 108  112          /* LEDs */
 109      -        mac->ops.led_on = &ixgbe_led_on_generic;
 110      -        mac->ops.led_off = &ixgbe_led_off_generic;
 111      -        mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
 112      -        mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
      113 +        mac->ops.led_on = ixgbe_led_on_generic;
      114 +        mac->ops.led_off = ixgbe_led_off_generic;
      115 +        mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
      116 +        mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
 113  117  
 114  118          /* RAR, Multicast, VLAN */
 115      -        mac->ops.set_rar = &ixgbe_set_rar_generic;
 116      -        mac->ops.clear_rar = &ixgbe_clear_rar_generic;
      119 +        mac->ops.set_rar = ixgbe_set_rar_generic;
      120 +        mac->ops.clear_rar = ixgbe_clear_rar_generic;
 117  121          mac->ops.insert_mac_addr = NULL;
 118  122          mac->ops.set_vmdq = NULL;
 119  123          mac->ops.clear_vmdq = NULL;
 120      -        mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
 121      -        mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
 122      -        mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
 123      -        mac->ops.enable_mc = &ixgbe_enable_mc_generic;
 124      -        mac->ops.disable_mc = &ixgbe_disable_mc_generic;
      124 +        mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
      125 +        mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
      126 +        mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
      127 +        mac->ops.enable_mc = ixgbe_enable_mc_generic;
      128 +        mac->ops.disable_mc = ixgbe_disable_mc_generic;
 125  129          mac->ops.clear_vfta = NULL;
 126  130          mac->ops.set_vfta = NULL;
 127  131          mac->ops.set_vlvf = NULL;
 128  132          mac->ops.init_uta_tables = NULL;
      133 +        mac->ops.enable_rx = ixgbe_enable_rx_generic;
      134 +        mac->ops.disable_rx = ixgbe_disable_rx_generic;
 129  135  
 130  136          /* Flow Control */
 131      -        mac->ops.fc_enable = &ixgbe_fc_enable_generic;
      137 +        mac->ops.fc_enable = ixgbe_fc_enable_generic;
      138 +        mac->ops.setup_fc = ixgbe_setup_fc_generic;
 132  139  
 133  140          /* Link */
 134  141          mac->ops.get_link_capabilities = NULL;
 135  142          mac->ops.setup_link = NULL;
 136  143          mac->ops.check_link = NULL;
      144 +        mac->ops.dmac_config = NULL;
      145 +        mac->ops.dmac_update_tcs = NULL;
      146 +        mac->ops.dmac_config_tcs = NULL;
 137  147  
 138  148          return IXGBE_SUCCESS;
 139  149  }
 140  150  
 141  151  /**
 142      - *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
 143      - *  control
 144      - *  @hw: pointer to hardware structure
      152 + * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
      153 + * of flow control
      154 + * @hw: pointer to hardware structure
 145  155   *
 146      - *  There are several phys that do not support autoneg flow control. This
 147      - *  function check the device id to see if the associated phy supports
 148      - *  autoneg flow control.
      156 + * This function returns TRUE if the device supports flow control
      157 + * autonegotiation, and FALSE if it does not.
      158 + *
 149  159   **/
 150      -static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
      160 +bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
 151  161  {
      162 +        bool supported = FALSE;
      163 +        ixgbe_link_speed speed;
      164 +        bool link_up;
 152  165  
 153  166          DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
 154  167  
 155      -        switch (hw->device_id) {
 156      -        case IXGBE_DEV_ID_X540T:
 157      -        case IXGBE_DEV_ID_X540T1:
 158      -                return IXGBE_SUCCESS;
 159      -        case IXGBE_DEV_ID_82599_T3_LOM:
 160      -                return IXGBE_SUCCESS;
      168 +        switch (hw->phy.media_type) {
      169 +        case ixgbe_media_type_fiber_fixed:
      170 +        case ixgbe_media_type_fiber_qsfp:
      171 +        case ixgbe_media_type_fiber:
      172 +                hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
      173 +                /* if link is down, assume supported */
      174 +                if (link_up)
      175 +                        supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
      176 +                                TRUE : FALSE;
      177 +                else
      178 +                        supported = TRUE;
      179 +                break;
      180 +        case ixgbe_media_type_backplane:
      181 +                supported = TRUE;
      182 +                break;
      183 +        case ixgbe_media_type_copper:
      184 +                /* only some copper devices support flow control autoneg */
      185 +                switch (hw->device_id) {
      186 +                case IXGBE_DEV_ID_82599_T3_LOM:
      187 +                case IXGBE_DEV_ID_X540T:
      188 +                case IXGBE_DEV_ID_X540T1:
      189 +                case IXGBE_DEV_ID_X540_BYPASS:
      190 +                case IXGBE_DEV_ID_X550T:
      191 +                case IXGBE_DEV_ID_X550T1:
      192 +                case IXGBE_DEV_ID_X550EM_X_10G_T:
      193 +                        supported = TRUE;
      194 +                        break;
      195 +                default:
      196 +                        supported = FALSE;
      197 +                }
 161  198          default:
 162      -                return IXGBE_ERR_FC_NOT_SUPPORTED;
      199 +                break;
 163  200          }
      201 +
      202 +        if (!supported) {
      203 +                ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
      204 +                      "Device %x does not support flow control autoneg",
      205 +                      hw->device_id);
      206 +        }
      207 +
      208 +        return supported;
 164  209  }
 165  210  
 166  211  /**
 167      - *  ixgbe_setup_fc - Set up flow control
      212 + *  ixgbe_setup_fc_generic - Set up flow control
 168  213   *  @hw: pointer to hardware structure
 169  214   *
 170  215   *  Called at init time to set up flow control.
 171  216   **/
 172      -static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
      217 +s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
 173  218  {
 174  219          s32 ret_val = IXGBE_SUCCESS;
 175  220          u32 reg = 0, reg_bp = 0;
 176  221          u16 reg_cu = 0;
      222 +        bool locked = FALSE;
 177  223  
 178      -        DEBUGFUNC("ixgbe_setup_fc");
      224 +        DEBUGFUNC("ixgbe_setup_fc_generic");
 179  225  
 180      -        /*
 181      -         * Validate the requested mode.  Strict IEEE mode does not allow
 182      -         * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
 183      -         */
      226 +        /* Validate the requested mode */
 184  227          if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 185      -                DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
      228 +                ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
      229 +                           "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 186  230                  ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 187  231                  goto out;
 188  232          }
 189  233  
 190  234          /*
 191  235           * 10gig parts do not have a word in the EEPROM to determine the
 192  236           * default flow control setting, so we explicitly set it to full.
 193  237           */
 194  238          if (hw->fc.requested_mode == ixgbe_fc_default)
 195  239                  hw->fc.requested_mode = ixgbe_fc_full;
 196  240  
 197  241          /*
 198  242           * Set up the 1G and 10G flow control advertisement registers so the
 199  243           * HW will be able to do fc autoneg once the cable is plugged in.  If
 200  244           * we link at 10G, the 1G advertisement is harmless and vice versa.
 201  245           */
 202  246          switch (hw->phy.media_type) {
 203      -        case ixgbe_media_type_fiber:
 204  247          case ixgbe_media_type_backplane:
      248 +                /* some MAC's need RMW protection on AUTOC */
      249 +                ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
      250 +                if (ret_val != IXGBE_SUCCESS)
      251 +                        goto out;
      252 +
      253 +                /* only backplane uses autoc so fall though */
      254 +        case ixgbe_media_type_fiber_fixed:
      255 +        case ixgbe_media_type_fiber_qsfp:
      256 +        case ixgbe_media_type_fiber:
 205  257                  reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 206      -                reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
      258 +
 207  259                  break;
 208  260          case ixgbe_media_type_copper:
 209  261                  hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
 210  262                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
 211  263                  break;
 212  264          default:
 213  265                  break;
 214  266          }
 215  267  
 216  268          /*
↓ open down ↓ 44 lines elided ↑ open up ↑
 261  313          case ixgbe_fc_full:
 262  314                  /* Flow control (both Rx and Tx) is enabled by SW override. */
 263  315                  reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
 264  316                  if (hw->phy.media_type == ixgbe_media_type_backplane)
 265  317                          reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
 266  318                                    IXGBE_AUTOC_ASM_PAUSE;
 267  319                  else if (hw->phy.media_type == ixgbe_media_type_copper)
 268  320                          reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
 269  321                  break;
 270  322          default:
 271      -                DEBUGOUT("Flow control param set incorrectly\n");
      323 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
      324 +                             "Flow control param set incorrectly\n");
 272  325                  ret_val = IXGBE_ERR_CONFIG;
 273  326                  goto out;
      327 +                break;
 274  328          }
 275  329  
 276      -        if (hw->mac.type != ixgbe_mac_X540) {
      330 +        if (hw->mac.type < ixgbe_mac_X540) {
 277  331                  /*
 278  332                   * Enable auto-negotiation between the MAC & PHY;
 279  333                   * the MAC will advertise clause 37 flow control.
 280  334                   */
 281  335                  IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
 282  336                  reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 283  337  
 284  338                  /* Disable AN timeout */
 285  339                  if (hw->fc.strict_ieee)
 286  340                          reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
↓ open down ↓ 2 lines elided ↑ open up ↑
 289  343                  DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
 290  344          }
 291  345  
 292  346          /*
 293  347           * AUTOC restart handles negotiation of 1G and 10G on backplane
 294  348           * and copper. There is no need to set the PCS1GCTL register.
 295  349           *
 296  350           */
 297  351          if (hw->phy.media_type == ixgbe_media_type_backplane) {
 298  352                  reg_bp |= IXGBE_AUTOC_AN_RESTART;
 299      -                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
      353 +                ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
      354 +                if (ret_val)
      355 +                        goto out;
 300  356          } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
 301      -                    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
      357 +                    (ixgbe_device_supports_autoneg_fc(hw))) {
 302  358                  hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
 303  359                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
 304  360          }
 305  361  
 306      -        DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
      362 +        DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
 307  363  out:
 308  364          return ret_val;
 309  365  }
 310  366  
 311  367  /**
 312  368   *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
 313  369   *  @hw: pointer to hardware structure
 314  370   *
 315  371   *  Starts the hardware by filling the bus info structure and media type, clears
 316  372   *  all on chip counters, initializes receive address registers, multicast
↓ open down ↓ 108 lines elided ↑ open up ↑
 425  481   *
 426  482   *  Clears all hardware statistics counters by reading them from the hardware
 427  483   *  Statistics counters are clear on read.
 428  484   **/
 429  485  s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 430  486  {
 431  487          u16 i = 0;
 432  488  
 433  489          DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
 434  490  
 435      -        (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
 436      -        (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
 437      -        (void) IXGBE_READ_REG(hw, IXGBE_ERRBC);
 438      -        (void) IXGBE_READ_REG(hw, IXGBE_MSPDC);
      491 +        IXGBE_READ_REG(hw, IXGBE_CRCERRS);
      492 +        IXGBE_READ_REG(hw, IXGBE_ILLERRC);
      493 +        IXGBE_READ_REG(hw, IXGBE_ERRBC);
      494 +        IXGBE_READ_REG(hw, IXGBE_MSPDC);
 439  495          for (i = 0; i < 8; i++)
 440      -                (void) IXGBE_READ_REG(hw, IXGBE_MPC(i));
      496 +                IXGBE_READ_REG(hw, IXGBE_MPC(i));
 441  497  
 442      -        (void) IXGBE_READ_REG(hw, IXGBE_MLFC);
 443      -        (void) IXGBE_READ_REG(hw, IXGBE_MRFC);
 444      -        (void) IXGBE_READ_REG(hw, IXGBE_RLEC);
 445      -        (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC);
 446      -        (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
      498 +        IXGBE_READ_REG(hw, IXGBE_MLFC);
      499 +        IXGBE_READ_REG(hw, IXGBE_MRFC);
      500 +        IXGBE_READ_REG(hw, IXGBE_RLEC);
      501 +        IXGBE_READ_REG(hw, IXGBE_LXONTXC);
      502 +        IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
 447  503          if (hw->mac.type >= ixgbe_mac_82599EB) {
 448      -                (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
 449      -                (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
      504 +                IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
      505 +                IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 450  506          } else {
 451      -                (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC);
 452      -                (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
      507 +                IXGBE_READ_REG(hw, IXGBE_LXONRXC);
      508 +                IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 453  509          }
 454  510  
 455  511          for (i = 0; i < 8; i++) {
 456      -                (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
 457      -                (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
      512 +                IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
      513 +                IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
 458  514                  if (hw->mac.type >= ixgbe_mac_82599EB) {
 459      -                        (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
 460      -                        (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
      515 +                        IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
      516 +                        IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 461  517                  } else {
 462      -                        (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
 463      -                        (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
      518 +                        IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
      519 +                        IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 464  520                  }
 465  521          }
 466  522          if (hw->mac.type >= ixgbe_mac_82599EB)
 467  523                  for (i = 0; i < 8; i++)
 468      -                        (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
 469      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC64);
 470      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC127);
 471      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC255);
 472      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC511);
 473      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC1023);
 474      -        (void) IXGBE_READ_REG(hw, IXGBE_PRC1522);
 475      -        (void) IXGBE_READ_REG(hw, IXGBE_GPRC);
 476      -        (void) IXGBE_READ_REG(hw, IXGBE_BPRC);
 477      -        (void) IXGBE_READ_REG(hw, IXGBE_MPRC);
 478      -        (void) IXGBE_READ_REG(hw, IXGBE_GPTC);
 479      -        (void) IXGBE_READ_REG(hw, IXGBE_GORCL);
 480      -        (void) IXGBE_READ_REG(hw, IXGBE_GORCH);
 481      -        (void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
 482      -        (void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
      524 +                        IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
      525 +        IXGBE_READ_REG(hw, IXGBE_PRC64);
      526 +        IXGBE_READ_REG(hw, IXGBE_PRC127);
      527 +        IXGBE_READ_REG(hw, IXGBE_PRC255);
      528 +        IXGBE_READ_REG(hw, IXGBE_PRC511);
      529 +        IXGBE_READ_REG(hw, IXGBE_PRC1023);
      530 +        IXGBE_READ_REG(hw, IXGBE_PRC1522);
      531 +        IXGBE_READ_REG(hw, IXGBE_GPRC);
      532 +        IXGBE_READ_REG(hw, IXGBE_BPRC);
      533 +        IXGBE_READ_REG(hw, IXGBE_MPRC);
      534 +        IXGBE_READ_REG(hw, IXGBE_GPTC);
      535 +        IXGBE_READ_REG(hw, IXGBE_GORCL);
      536 +        IXGBE_READ_REG(hw, IXGBE_GORCH);
      537 +        IXGBE_READ_REG(hw, IXGBE_GOTCL);
      538 +        IXGBE_READ_REG(hw, IXGBE_GOTCH);
 483  539          if (hw->mac.type == ixgbe_mac_82598EB)
 484  540                  for (i = 0; i < 8; i++)
 485      -                        (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
 486      -        (void) IXGBE_READ_REG(hw, IXGBE_RUC);
 487      -        (void) IXGBE_READ_REG(hw, IXGBE_RFC);
 488      -        (void) IXGBE_READ_REG(hw, IXGBE_ROC);
 489      -        (void) IXGBE_READ_REG(hw, IXGBE_RJC);
 490      -        (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC);
 491      -        (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC);
 492      -        (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC);
 493      -        (void) IXGBE_READ_REG(hw, IXGBE_TORL);
 494      -        (void) IXGBE_READ_REG(hw, IXGBE_TORH);
 495      -        (void) IXGBE_READ_REG(hw, IXGBE_TPR);
 496      -        (void) IXGBE_READ_REG(hw, IXGBE_TPT);
 497      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC64);
 498      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC127);
 499      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC255);
 500      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC511);
 501      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC1023);
 502      -        (void) IXGBE_READ_REG(hw, IXGBE_PTC1522);
 503      -        (void) IXGBE_READ_REG(hw, IXGBE_MPTC);
 504      -        (void) IXGBE_READ_REG(hw, IXGBE_BPTC);
      541 +                        IXGBE_READ_REG(hw, IXGBE_RNBC(i));
      542 +        IXGBE_READ_REG(hw, IXGBE_RUC);
      543 +        IXGBE_READ_REG(hw, IXGBE_RFC);
      544 +        IXGBE_READ_REG(hw, IXGBE_ROC);
      545 +        IXGBE_READ_REG(hw, IXGBE_RJC);
      546 +        IXGBE_READ_REG(hw, IXGBE_MNGPRC);
      547 +        IXGBE_READ_REG(hw, IXGBE_MNGPDC);
      548 +        IXGBE_READ_REG(hw, IXGBE_MNGPTC);
      549 +        IXGBE_READ_REG(hw, IXGBE_TORL);
      550 +        IXGBE_READ_REG(hw, IXGBE_TORH);
      551 +        IXGBE_READ_REG(hw, IXGBE_TPR);
      552 +        IXGBE_READ_REG(hw, IXGBE_TPT);
      553 +        IXGBE_READ_REG(hw, IXGBE_PTC64);
      554 +        IXGBE_READ_REG(hw, IXGBE_PTC127);
      555 +        IXGBE_READ_REG(hw, IXGBE_PTC255);
      556 +        IXGBE_READ_REG(hw, IXGBE_PTC511);
      557 +        IXGBE_READ_REG(hw, IXGBE_PTC1023);
      558 +        IXGBE_READ_REG(hw, IXGBE_PTC1522);
      559 +        IXGBE_READ_REG(hw, IXGBE_MPTC);
      560 +        IXGBE_READ_REG(hw, IXGBE_BPTC);
 505  561          for (i = 0; i < 16; i++) {
 506      -                (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i));
 507      -                (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i));
      562 +                IXGBE_READ_REG(hw, IXGBE_QPRC(i));
      563 +                IXGBE_READ_REG(hw, IXGBE_QPTC(i));
 508  564                  if (hw->mac.type >= ixgbe_mac_82599EB) {
 509      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
 510      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
 511      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
 512      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
 513      -                        (void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
      565 +                        IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
      566 +                        IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
      567 +                        IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
      568 +                        IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
      569 +                        IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
 514  570                  } else {
 515      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i));
 516      -                        (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i));
      571 +                        IXGBE_READ_REG(hw, IXGBE_QBRC(i));
      572 +                        IXGBE_READ_REG(hw, IXGBE_QBTC(i));
 517  573                  }
 518  574          }
 519  575  
 520      -        if (hw->mac.type == ixgbe_mac_X540) {
      576 +        if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
 521  577                  if (hw->phy.id == 0)
 522      -                        (void) ixgbe_identify_phy(hw);
      578 +                        ixgbe_identify_phy(hw);
 523  579                  hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
 524  580                                       IXGBE_MDIO_PCS_DEV_TYPE, &i);
 525  581                  hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
 526  582                                       IXGBE_MDIO_PCS_DEV_TYPE, &i);
 527  583                  hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
 528  584                                       IXGBE_MDIO_PCS_DEV_TYPE, &i);
 529  585                  hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
 530  586                                       IXGBE_MDIO_PCS_DEV_TYPE, &i);
 531  587          }
 532  588  
↓ open down ↓ 139 lines elided ↑ open up ↑
 672  728          if (ret_val) {
 673  729                  DEBUGOUT("NVM Read Error\n");
 674  730                  return ret_val;
 675  731          }
 676  732          *pba_num |= data;
 677  733  
 678  734          return IXGBE_SUCCESS;
 679  735  }
 680  736  
 681  737  /**
      738 + *  ixgbe_read_pba_raw
      739 + *  @hw: pointer to the HW structure
      740 + *  @eeprom_buf: optional pointer to EEPROM image
      741 + *  @eeprom_buf_size: size of EEPROM image in words
      742 + *  @max_pba_block_size: PBA block size limit
      743 + *  @pba: pointer to output PBA structure
      744 + *
      745 + *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
      746 + *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
      747 + *
      748 + **/
      749 +s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
      750 +                       u32 eeprom_buf_size, u16 max_pba_block_size,
      751 +                       struct ixgbe_pba *pba)
      752 +{
      753 +        s32 ret_val;
      754 +        u16 pba_block_size;
      755 +
      756 +        if (pba == NULL)
      757 +                return IXGBE_ERR_PARAM;
      758 +
      759 +        if (eeprom_buf == NULL) {
      760 +                ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
      761 +                                                     &pba->word[0]);
      762 +                if (ret_val)
      763 +                        return ret_val;
      764 +        } else {
      765 +                if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
      766 +                        pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
      767 +                        pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
      768 +                } else {
      769 +                        return IXGBE_ERR_PARAM;
      770 +                }
      771 +        }
      772 +
      773 +        if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
      774 +                if (pba->pba_block == NULL)
      775 +                        return IXGBE_ERR_PARAM;
      776 +
      777 +                ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
      778 +                                                   eeprom_buf_size,
      779 +                                                   &pba_block_size);
      780 +                if (ret_val)
      781 +                        return ret_val;
      782 +
      783 +                if (pba_block_size > max_pba_block_size)
      784 +                        return IXGBE_ERR_PARAM;
      785 +
      786 +                if (eeprom_buf == NULL) {
      787 +                        ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
      788 +                                                             pba_block_size,
      789 +                                                             pba->pba_block);
      790 +                        if (ret_val)
      791 +                                return ret_val;
      792 +                } else {
      793 +                        if (eeprom_buf_size > (u32)(pba->word[1] +
      794 +                                              pba_block_size)) {
      795 +                                memcpy(pba->pba_block,
      796 +                                       &eeprom_buf[pba->word[1]],
      797 +                                       pba_block_size * sizeof(u16));
      798 +                        } else {
      799 +                                return IXGBE_ERR_PARAM;
      800 +                        }
      801 +                }
      802 +        }
      803 +
      804 +        return IXGBE_SUCCESS;
      805 +}
      806 +
      807 +/**
      808 + *  ixgbe_write_pba_raw
      809 + *  @hw: pointer to the HW structure
      810 + *  @eeprom_buf: optional pointer to EEPROM image
      811 + *  @eeprom_buf_size: size of EEPROM image in words
      812 + *  @pba: pointer to PBA structure
      813 + *
      814 + *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
      815 + *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
      816 + *
      817 + **/
      818 +s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
      819 +                        u32 eeprom_buf_size, struct ixgbe_pba *pba)
      820 +{
      821 +        s32 ret_val;
      822 +
      823 +        if (pba == NULL)
      824 +                return IXGBE_ERR_PARAM;
      825 +
      826 +        if (eeprom_buf == NULL) {
      827 +                ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
      828 +                                                      &pba->word[0]);
      829 +                if (ret_val)
      830 +                        return ret_val;
      831 +        } else {
      832 +                if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
      833 +                        eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
      834 +                        eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
      835 +                } else {
      836 +                        return IXGBE_ERR_PARAM;
      837 +                }
      838 +        }
      839 +
      840 +        if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
      841 +                if (pba->pba_block == NULL)
      842 +                        return IXGBE_ERR_PARAM;
      843 +
      844 +                if (eeprom_buf == NULL) {
      845 +                        ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
      846 +                                                              pba->pba_block[0],
      847 +                                                              pba->pba_block);
      848 +                        if (ret_val)
      849 +                                return ret_val;
      850 +                } else {
      851 +                        if (eeprom_buf_size > (u32)(pba->word[1] +
      852 +                                              pba->pba_block[0])) {
      853 +                                memcpy(&eeprom_buf[pba->word[1]],
      854 +                                       pba->pba_block,
      855 +                                       pba->pba_block[0] * sizeof(u16));
      856 +                        } else {
      857 +                                return IXGBE_ERR_PARAM;
      858 +                        }
      859 +                }
      860 +        }
      861 +
      862 +        return IXGBE_SUCCESS;
      863 +}
      864 +
      865 +/**
      866 + *  ixgbe_get_pba_block_size
      867 + *  @hw: pointer to the HW structure
      868 + *  @eeprom_buf: optional pointer to EEPROM image
      869 + *  @eeprom_buf_size: size of EEPROM image in words
      870 + *  @pba_data_size: pointer to output variable
      871 + *
      872 + *  Returns the size of the PBA block in words. Function operates on EEPROM
      873 + *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
      874 + *  EEPROM device.
      875 + *
      876 + **/
      877 +s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
      878 +                             u32 eeprom_buf_size, u16 *pba_block_size)
      879 +{
      880 +        s32 ret_val;
      881 +        u16 pba_word[2];
      882 +        u16 length;
      883 +
      884 +        DEBUGFUNC("ixgbe_get_pba_block_size");
      885 +
      886 +        if (eeprom_buf == NULL) {
      887 +                ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
      888 +                                                     &pba_word[0]);
      889 +                if (ret_val)
      890 +                        return ret_val;
      891 +        } else {
      892 +                if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
      893 +                        pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
      894 +                        pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
      895 +                } else {
      896 +                        return IXGBE_ERR_PARAM;
      897 +                }
      898 +        }
      899 +
      900 +        if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
      901 +                if (eeprom_buf == NULL) {
      902 +                        ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
      903 +                                                      &length);
      904 +                        if (ret_val)
      905 +                                return ret_val;
      906 +                } else {
      907 +                        if (eeprom_buf_size > pba_word[1])
      908 +                                length = eeprom_buf[pba_word[1] + 0];
      909 +                        else
      910 +                                return IXGBE_ERR_PARAM;
      911 +                }
      912 +
      913 +                if (length == 0xFFFF || length == 0)
      914 +                        return IXGBE_ERR_PBA_SECTION;
      915 +        } else {
      916 +                /* PBA number in legacy format, there is no PBA Block. */
      917 +                length = 0;
      918 +        }
      919 +
      920 +        if (pba_block_size != NULL)
      921 +                *pba_block_size = length;
      922 +
      923 +        return IXGBE_SUCCESS;
      924 +}
      925 +
      926 +/**
 682  927   *  ixgbe_get_mac_addr_generic - Generic get MAC address
 683  928   *  @hw: pointer to hardware structure
 684  929   *  @mac_addr: Adapter MAC address
 685  930   *
 686  931   *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
 687  932   *  A reset of the adapter must be performed prior to calling this function
 688  933   *  in order for the MAC address to have been loaded from the EEPROM into RAR0
 689  934   **/
 690  935  s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
 691  936  {
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 701  946          for (i = 0; i < 4; i++)
 702  947                  mac_addr[i] = (u8)(rar_low >> (i*8));
 703  948  
 704  949          for (i = 0; i < 2; i++)
 705  950                  mac_addr[i+4] = (u8)(rar_high >> (i*8));
 706  951  
 707  952          return IXGBE_SUCCESS;
 708  953  }
 709  954  
 710  955  /**
 711      - *  ixgbe_get_bus_info_generic - Generic set PCI bus info
      956 + *  ixgbe_set_pci_config_data_generic - Generic store PCI bus info
 712  957   *  @hw: pointer to hardware structure
      958 + *  @link_status: the link status returned by the PCI config space
 713  959   *
 714      - *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
      960 + *  Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
 715  961   **/
 716      -s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
      962 +void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
 717  963  {
 718  964          struct ixgbe_mac_info *mac = &hw->mac;
 719      -        u16 link_status;
 720  965  
 721      -        DEBUGFUNC("ixgbe_get_bus_info_generic");
      966 +        if (hw->bus.type == ixgbe_bus_type_unknown)
      967 +                hw->bus.type = ixgbe_bus_type_pci_express;
 722  968  
 723      -        hw->bus.type = ixgbe_bus_type_pci_express;
 724      -
 725      -        /* Get the negotiated link width and speed from PCI config space */
 726      -        link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
 727      -
 728  969          switch (link_status & IXGBE_PCI_LINK_WIDTH) {
 729  970          case IXGBE_PCI_LINK_WIDTH_1:
 730  971                  hw->bus.width = ixgbe_bus_width_pcie_x1;
 731  972                  break;
 732  973          case IXGBE_PCI_LINK_WIDTH_2:
 733  974                  hw->bus.width = ixgbe_bus_width_pcie_x2;
 734  975                  break;
 735  976          case IXGBE_PCI_LINK_WIDTH_4:
 736  977                  hw->bus.width = ixgbe_bus_width_pcie_x4;
 737  978                  break;
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 752  993                  break;
 753  994          case IXGBE_PCI_LINK_SPEED_8000:
 754  995                  hw->bus.speed = ixgbe_bus_speed_8000;
 755  996                  break;
 756  997          default:
 757  998                  hw->bus.speed = ixgbe_bus_speed_unknown;
 758  999                  break;
 759 1000          }
 760 1001  
 761 1002          mac->ops.set_lan_id(hw);
     1003 +}
 762 1004  
     1005 +/**
     1006 + *  ixgbe_get_bus_info_generic - Generic set PCI bus info
     1007 + *  @hw: pointer to hardware structure
     1008 + *
     1009 + *  Gets the PCI bus info (speed, width, type) then calls helper function to
     1010 + *  store this data within the ixgbe_hw structure.
     1011 + **/
     1012 +s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
     1013 +{
     1014 +        u16 link_status;
     1015 +
     1016 +        DEBUGFUNC("ixgbe_get_bus_info_generic");
     1017 +
     1018 +        /* Get the negotiated link width and speed from PCI config space */
     1019 +        link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
     1020 +
     1021 +        ixgbe_set_pci_config_data_generic(hw, link_status);
     1022 +
 763 1023          return IXGBE_SUCCESS;
 764 1024  }
 765 1025  
 766 1026  /**
 767 1027   *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
 768 1028   *  @hw: pointer to the HW structure
 769 1029   *
 770 1030   *  Determines the LAN function id by reading memory-mapped registers
 771 1031   *  and swaps the port value if requested.
 772 1032   **/
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 775 1035          struct ixgbe_bus_info *bus = &hw->bus;
 776 1036          u32 reg;
 777 1037  
 778 1038          DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
 779 1039  
 780 1040          reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
 781 1041          bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
 782 1042          bus->lan_id = bus->func;
 783 1043  
 784 1044          /* check for a port swap */
 785      -        reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
     1045 +        reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
 786 1046          if (reg & IXGBE_FACTPS_LFS)
 787 1047                  bus->func ^= 0x1;
 788 1048  }
 789 1049  
 790 1050  /**
 791 1051   *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
 792 1052   *  @hw: pointer to hardware structure
 793 1053   *
 794 1054   *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
 795 1055   *  disables transmit and receive units. The adapter_stopped flag is used by
↓ open down ↓ 7 lines elided ↑ open up ↑
 803 1063  
 804 1064          DEBUGFUNC("ixgbe_stop_adapter_generic");
 805 1065  
 806 1066          /*
 807 1067           * Set the adapter_stopped flag so other driver functions stop touching
 808 1068           * the hardware
 809 1069           */
 810 1070          hw->adapter_stopped = TRUE;
 811 1071  
 812 1072          /* Disable the receive unit */
 813      -        IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
     1073 +        ixgbe_disable_rx(hw);
 814 1074  
 815 1075          /* Clear interrupt mask to stop interrupts from being generated */
 816 1076          IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
 817 1077  
 818 1078          /* Clear any pending interrupts, flush previous writes */
 819      -        (void) IXGBE_READ_REG(hw, IXGBE_EICR);
     1079 +        IXGBE_READ_REG(hw, IXGBE_EICR);
 820 1080  
 821 1081          /* Disable the transmit unit.  Each queue must be disabled. */
 822 1082          for (i = 0; i < hw->mac.max_tx_queues; i++)
 823 1083                  IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
 824 1084  
 825 1085          /* Disable the receive unit by stopping each queue */
 826 1086          for (i = 0; i < hw->mac.max_rx_queues; i++) {
 827 1087                  reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 828 1088                  reg_val &= ~IXGBE_RXDCTL_ENABLE;
 829 1089                  reg_val |= IXGBE_RXDCTL_SWFLSH;
 830 1090                  IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
 831 1091          }
 832 1092  
 833 1093          /* flush all queues disables */
 834 1094          IXGBE_WRITE_FLUSH(hw);
 835 1095          msec_delay(2);
 836 1096  
 837 1097          /*
 838      -         * Prevent the PCI-E bus from from hanging by disabling PCI-E master
     1098 +         * Prevent the PCI-E bus from hanging by disabling PCI-E master
 839 1099           * access and verify no pending requests
 840 1100           */
 841 1101          return ixgbe_disable_pcie_master(hw);
 842 1102  }
 843 1103  
 844 1104  /**
 845 1105   *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
 846 1106   *  @hw: pointer to hardware structure
 847 1107   *  @index: led number to turn on
 848 1108   **/
↓ open down ↓ 52 lines elided ↑ open up ↑
 901 1161                  /* Set default semaphore delay to 10ms which is a well
 902 1162                   * tested value */
 903 1163                  eeprom->semaphore_delay = 10;
 904 1164                  /* Clear EEPROM page size, it will be initialized as needed */
 905 1165                  eeprom->word_page_size = 0;
 906 1166  
 907 1167                  /*
 908 1168                   * Check for EEPROM present first.
 909 1169                   * If not present leave as none
 910 1170                   */
 911      -                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     1171 +                eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 912 1172                  if (eec & IXGBE_EEC_PRES) {
 913 1173                          eeprom->type = ixgbe_eeprom_spi;
 914 1174  
 915 1175                          /*
 916 1176                           * SPI EEPROM is assumed here.  This code would need to
 917 1177                           * change if a future EEPROM is not SPI.
 918 1178                           */
 919 1179                          eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 920 1180                                              IXGBE_EEC_SIZE_SHIFT);
 921 1181                          eeprom->word_size = 1 << (eeprom_size +
↓ open down ↓ 40 lines elided ↑ open up ↑
 962 1222                  status = IXGBE_ERR_EEPROM;
 963 1223                  goto out;
 964 1224          }
 965 1225  
 966 1226          /*
 967 1227           * The EEPROM page size cannot be queried from the chip. We do lazy
 968 1228           * initialization. It is worth to do that when we write large buffer.
 969 1229           */
 970 1230          if ((hw->eeprom.word_page_size == 0) &&
 971 1231              (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
 972      -                status = ixgbe_detect_eeprom_page_size_generic(hw, offset);
 973      -        if (status != IXGBE_SUCCESS)
 974      -                goto out;
     1232 +                ixgbe_detect_eeprom_page_size_generic(hw, offset);
 975 1233  
 976 1234          /*
 977 1235           * We cannot hold synchronization semaphores for too long
 978 1236           * to avoid other entity starvation. However it is more efficient
 979 1237           * to read in bursts than synchronizing access for each word.
 980 1238           */
 981 1239          for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
 982 1240                  count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
 983 1241                          IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
 984 1242                  status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
↓ open down ↓ 268 lines elided ↑ open up ↑
1253 1511          u32 eerd;
1254 1512          s32 status = IXGBE_SUCCESS;
1255 1513          u32 i;
1256 1514  
1257 1515          DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1258 1516  
1259 1517          hw->eeprom.ops.init_params(hw);
1260 1518  
1261 1519          if (words == 0) {
1262 1520                  status = IXGBE_ERR_INVALID_ARGUMENT;
     1521 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1263 1522                  goto out;
1264 1523          }
1265 1524  
1266 1525          if (offset >= hw->eeprom.word_size) {
1267 1526                  status = IXGBE_ERR_EEPROM;
     1527 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1268 1528                  goto out;
1269 1529          }
1270 1530  
1271 1531          for (i = 0; i < words; i++) {
1272      -                eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
     1532 +                eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1273 1533                         IXGBE_EEPROM_RW_REG_START;
1274 1534  
1275 1535                  IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1276 1536                  status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1277 1537  
1278 1538                  if (status == IXGBE_SUCCESS) {
1279 1539                          data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1280 1540                                     IXGBE_EEPROM_RW_REG_DATA);
1281 1541                  } else {
1282 1542                          DEBUGOUT("Eeprom read timed out\n");
↓ open down ↓ 76 lines elided ↑ open up ↑
1359 1619          u32 eewr;
1360 1620          s32 status = IXGBE_SUCCESS;
1361 1621          u16 i;
1362 1622  
1363 1623          DEBUGFUNC("ixgbe_write_eewr_generic");
1364 1624  
1365 1625          hw->eeprom.ops.init_params(hw);
1366 1626  
1367 1627          if (words == 0) {
1368 1628                  status = IXGBE_ERR_INVALID_ARGUMENT;
     1629 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1369 1630                  goto out;
1370 1631          }
1371 1632  
1372 1633          if (offset >= hw->eeprom.word_size) {
1373 1634                  status = IXGBE_ERR_EEPROM;
     1635 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1374 1636                  goto out;
1375 1637          }
1376 1638  
1377 1639          for (i = 0; i < words; i++) {
1378 1640                  eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1379 1641                          (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1380 1642                          IXGBE_EEPROM_RW_REG_START;
1381 1643  
1382 1644                  status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1383 1645                  if (status != IXGBE_SUCCESS) {
↓ open down ↓ 48 lines elided ↑ open up ↑
1432 1694                          reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1433 1695                  else
1434 1696                          reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1435 1697  
1436 1698                  if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1437 1699                          status = IXGBE_SUCCESS;
1438 1700                          break;
1439 1701                  }
1440 1702                  usec_delay(5);
1441 1703          }
     1704 +
     1705 +        if (i == IXGBE_EERD_EEWR_ATTEMPTS)
     1706 +                ERROR_REPORT1(IXGBE_ERROR_POLLING,
     1707 +                             "EEPROM read/write done polling timed out");
     1708 +
1442 1709          return status;
1443 1710  }
1444 1711  
1445 1712  /**
1446 1713   *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1447 1714   *  @hw: pointer to hardware structure
1448 1715   *
1449 1716   *  Prepares EEPROM for access using bit-bang method. This function should
1450 1717   *  be called before issuing a command to the EEPROM.
1451 1718   **/
↓ open down ↓ 3 lines elided ↑ open up ↑
1455 1722          u32 eec;
1456 1723          u32 i;
1457 1724  
1458 1725          DEBUGFUNC("ixgbe_acquire_eeprom");
1459 1726  
1460 1727          if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1461 1728              != IXGBE_SUCCESS)
1462 1729                  status = IXGBE_ERR_SWFW_SYNC;
1463 1730  
1464 1731          if (status == IXGBE_SUCCESS) {
1465      -                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     1732 +                eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1466 1733  
1467 1734                  /* Request EEPROM Access */
1468 1735                  eec |= IXGBE_EEC_REQ;
1469      -                IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1736 +                IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1470 1737  
1471 1738                  for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1472      -                        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     1739 +                        eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1473 1740                          if (eec & IXGBE_EEC_GNT)
1474 1741                                  break;
1475 1742                          usec_delay(5);
1476 1743                  }
1477 1744  
1478 1745                  /* Release if grant not acquired */
1479 1746                  if (!(eec & IXGBE_EEC_GNT)) {
1480 1747                          eec &= ~IXGBE_EEC_REQ;
1481      -                        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1748 +                        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1482 1749                          DEBUGOUT("Could not acquire EEPROM grant\n");
1483 1750  
1484 1751                          hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1485 1752                          status = IXGBE_ERR_EEPROM;
1486 1753                  }
1487 1754  
1488 1755                  /* Setup EEPROM for Read/Write */
1489 1756                  if (status == IXGBE_SUCCESS) {
1490 1757                          /* Clear CS and SK */
1491 1758                          eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1492      -                        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1759 +                        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1493 1760                          IXGBE_WRITE_FLUSH(hw);
1494 1761                          usec_delay(1);
1495 1762                  }
1496 1763          }
1497 1764          return status;
1498 1765  }
1499 1766  
1500 1767  /**
1501 1768   *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
1502 1769   *  @hw: pointer to hardware structure
↓ open down ↓ 9 lines elided ↑ open up ↑
1512 1779  
1513 1780          DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1514 1781  
1515 1782  
1516 1783          /* Get SMBI software semaphore between device drivers first */
1517 1784          for (i = 0; i < timeout; i++) {
1518 1785                  /*
1519 1786                   * If the SMBI bit is 0 when we read it, then the bit will be
1520 1787                   * set and we have the semaphore
1521 1788                   */
1522      -                swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
     1789 +                swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1523 1790                  if (!(swsm & IXGBE_SWSM_SMBI)) {
1524 1791                          status = IXGBE_SUCCESS;
1525 1792                          break;
1526 1793                  }
1527 1794                  usec_delay(50);
1528 1795          }
1529 1796  
1530 1797          if (i == timeout) {
1531 1798                  DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1532 1799                           "not granted.\n");
↓ open down ↓ 4 lines elided ↑ open up ↑
1537 1804                   * bits to free the driver to make progress
1538 1805                   */
1539 1806                  ixgbe_release_eeprom_semaphore(hw);
1540 1807  
1541 1808                  usec_delay(50);
1542 1809                  /*
1543 1810                   * one last try
1544 1811                   * If the SMBI bit is 0 when we read it, then the bit will be
1545 1812                   * set and we have the semaphore
1546 1813                   */
1547      -                swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
     1814 +                swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1548 1815                  if (!(swsm & IXGBE_SWSM_SMBI))
1549 1816                          status = IXGBE_SUCCESS;
1550 1817          }
1551 1818  
1552 1819          /* Now get the semaphore between SW/FW through the SWESMBI bit */
1553 1820          if (status == IXGBE_SUCCESS) {
1554 1821                  for (i = 0; i < timeout; i++) {
1555      -                        swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
     1822 +                        swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1556 1823  
1557 1824                          /* Set the SW EEPROM semaphore bit to request access */
1558 1825                          swsm |= IXGBE_SWSM_SWESMBI;
1559      -                        IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
     1826 +                        IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1560 1827  
1561 1828                          /*
1562 1829                           * If we set the bit successfully then we got the
1563 1830                           * semaphore.
1564 1831                           */
1565      -                        swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
     1832 +                        swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1566 1833                          if (swsm & IXGBE_SWSM_SWESMBI)
1567 1834                                  break;
1568 1835  
1569 1836                          usec_delay(50);
1570 1837                  }
1571 1838  
1572 1839                  /*
1573 1840                   * Release semaphores and return error if SW EEPROM semaphore
1574 1841                   * was not granted because we don't have access to the EEPROM
1575 1842                   */
1576 1843                  if (i >= timeout) {
1577      -                        DEBUGOUT("SWESMBI Software EEPROM semaphore "
1578      -                                 "not granted.\n");
     1844 +                        ERROR_REPORT1(IXGBE_ERROR_POLLING,
     1845 +                            "SWESMBI Software EEPROM semaphore not granted.\n");
1579 1846                          ixgbe_release_eeprom_semaphore(hw);
1580 1847                          status = IXGBE_ERR_EEPROM;
1581 1848                  }
1582 1849          } else {
1583      -                DEBUGOUT("Software semaphore SMBI between device drivers "
1584      -                         "not granted.\n");
     1850 +                ERROR_REPORT1(IXGBE_ERROR_POLLING,
     1851 +                             "Software semaphore SMBI between device drivers "
     1852 +                             "not granted.\n");
1585 1853          }
1586 1854  
1587 1855          return status;
1588 1856  }
1589 1857  
1590 1858  /**
1591 1859   *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
1592 1860   *  @hw: pointer to hardware structure
1593 1861   *
1594 1862   *  This function clears hardware semaphore bits.
↓ open down ↓ 32 lines elided ↑ open up ↑
1627 1895           */
1628 1896          for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1629 1897                  ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1630 1898                                              IXGBE_EEPROM_OPCODE_BITS);
1631 1899                  spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1632 1900                  if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1633 1901                          break;
1634 1902  
1635 1903                  usec_delay(5);
1636 1904                  ixgbe_standby_eeprom(hw);
1637      -        };
     1905 +        }
1638 1906  
1639 1907          /*
1640 1908           * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1641 1909           * devices (and only 0-5mSec on 5V devices)
1642 1910           */
1643 1911          if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1644 1912                  DEBUGOUT("SPI EEPROM Status error\n");
1645 1913                  status = IXGBE_ERR_EEPROM;
1646 1914          }
1647 1915  
↓ open down ↓ 3 lines elided ↑ open up ↑
1651 1919  /**
1652 1920   *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1653 1921   *  @hw: pointer to hardware structure
1654 1922   **/
1655 1923  static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1656 1924  {
1657 1925          u32 eec;
1658 1926  
1659 1927          DEBUGFUNC("ixgbe_standby_eeprom");
1660 1928  
1661      -        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     1929 +        eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1662 1930  
1663 1931          /* Toggle CS to flush commands */
1664 1932          eec |= IXGBE_EEC_CS;
1665      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1933 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1666 1934          IXGBE_WRITE_FLUSH(hw);
1667 1935          usec_delay(1);
1668 1936          eec &= ~IXGBE_EEC_CS;
1669      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1937 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1670 1938          IXGBE_WRITE_FLUSH(hw);
1671 1939          usec_delay(1);
1672 1940  }
1673 1941  
1674 1942  /**
1675 1943   *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1676 1944   *  @hw: pointer to hardware structure
1677 1945   *  @data: data to send to the EEPROM
1678 1946   *  @count: number of bits to shift out
1679 1947   **/
1680 1948  static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1681 1949                                          u16 count)
1682 1950  {
1683 1951          u32 eec;
1684 1952          u32 mask;
1685 1953          u32 i;
1686 1954  
1687 1955          DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1688 1956  
1689      -        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     1957 +        eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1690 1958  
1691 1959          /*
1692 1960           * Mask is used to shift "count" bits of "data" out to the EEPROM
1693 1961           * one bit at a time.  Determine the starting bit based on count
1694 1962           */
1695 1963          mask = 0x01 << (count - 1);
1696 1964  
1697 1965          for (i = 0; i < count; i++) {
1698 1966                  /*
1699 1967                   * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1700 1968                   * "1", and then raising and then lowering the clock (the SK
1701 1969                   * bit controls the clock input to the EEPROM).  A "0" is
1702 1970                   * shifted out to the EEPROM by setting "DI" to "0" and then
1703 1971                   * raising and then lowering the clock.
1704 1972                   */
1705 1973                  if (data & mask)
1706 1974                          eec |= IXGBE_EEC_DI;
1707 1975                  else
1708 1976                          eec &= ~IXGBE_EEC_DI;
1709 1977  
1710      -                IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1978 +                IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1711 1979                  IXGBE_WRITE_FLUSH(hw);
1712 1980  
1713 1981                  usec_delay(1);
1714 1982  
1715 1983                  ixgbe_raise_eeprom_clk(hw, &eec);
1716 1984                  ixgbe_lower_eeprom_clk(hw, &eec);
1717 1985  
1718 1986                  /*
1719 1987                   * Shift mask to signify next bit of data to shift in to the
1720 1988                   * EEPROM
1721 1989                   */
1722 1990                  mask = mask >> 1;
1723      -        };
     1991 +        }
1724 1992  
1725 1993          /* We leave the "DI" bit set to "0" when we leave this routine. */
1726 1994          eec &= ~IXGBE_EEC_DI;
1727      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     1995 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1728 1996          IXGBE_WRITE_FLUSH(hw);
1729 1997  }
1730 1998  
1731 1999  /**
1732 2000   *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1733 2001   *  @hw: pointer to hardware structure
1734 2002   **/
1735 2003  static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1736 2004  {
1737 2005          u32 eec;
↓ open down ↓ 2 lines elided ↑ open up ↑
1740 2008  
1741 2009          DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1742 2010  
1743 2011          /*
1744 2012           * In order to read a register from the EEPROM, we need to shift
1745 2013           * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1746 2014           * the clock input to the EEPROM (setting the SK bit), and then reading
1747 2015           * the value of the "DO" bit.  During this "shifting in" process the
1748 2016           * "DI" bit should always be clear.
1749 2017           */
1750      -        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     2018 +        eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1751 2019  
1752 2020          eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1753 2021  
1754 2022          for (i = 0; i < count; i++) {
1755 2023                  data = data << 1;
1756 2024                  ixgbe_raise_eeprom_clk(hw, &eec);
1757 2025  
1758      -                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     2026 +                eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1759 2027  
1760 2028                  eec &= ~(IXGBE_EEC_DI);
1761 2029                  if (eec & IXGBE_EEC_DO)
1762 2030                          data |= 1;
1763 2031  
1764 2032                  ixgbe_lower_eeprom_clk(hw, &eec);
1765 2033          }
1766 2034  
1767 2035          return data;
1768 2036  }
↓ open down ↓ 5 lines elided ↑ open up ↑
1774 2042   **/
1775 2043  static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1776 2044  {
1777 2045          DEBUGFUNC("ixgbe_raise_eeprom_clk");
1778 2046  
1779 2047          /*
1780 2048           * Raise the clock input to the EEPROM
1781 2049           * (setting the SK bit), then delay
1782 2050           */
1783 2051          *eec = *eec | IXGBE_EEC_SK;
1784      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
     2052 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
1785 2053          IXGBE_WRITE_FLUSH(hw);
1786 2054          usec_delay(1);
1787 2055  }
1788 2056  
1789 2057  /**
1790 2058   *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1791 2059   *  @hw: pointer to hardware structure
1792 2060   *  @eecd: EECD's current value
1793 2061   **/
1794 2062  static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1795 2063  {
1796 2064          DEBUGFUNC("ixgbe_lower_eeprom_clk");
1797 2065  
1798 2066          /*
1799 2067           * Lower the clock input to the EEPROM (clearing the SK bit), then
1800 2068           * delay
1801 2069           */
1802 2070          *eec = *eec & ~IXGBE_EEC_SK;
1803      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
     2071 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
1804 2072          IXGBE_WRITE_FLUSH(hw);
1805 2073          usec_delay(1);
1806 2074  }
1807 2075  
1808 2076  /**
1809 2077   *  ixgbe_release_eeprom - Release EEPROM, release semaphores
1810 2078   *  @hw: pointer to hardware structure
1811 2079   **/
1812 2080  static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1813 2081  {
1814 2082          u32 eec;
1815 2083  
1816 2084          DEBUGFUNC("ixgbe_release_eeprom");
1817 2085  
1818      -        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
     2086 +        eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1819 2087  
1820 2088          eec |= IXGBE_EEC_CS;  /* Pull CS high */
1821 2089          eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1822 2090  
1823      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     2091 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1824 2092          IXGBE_WRITE_FLUSH(hw);
1825 2093  
1826 2094          usec_delay(1);
1827 2095  
1828 2096          /* Stop requesting EEPROM access */
1829 2097          eec &= ~IXGBE_EEC_REQ;
1830      -        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
     2098 +        IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1831 2099  
1832 2100          hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1833 2101  
1834 2102          /* Delay before attempt to obtain semaphore again to allow FW access */
1835 2103          msec_delay(hw->eeprom.semaphore_delay);
1836 2104  }
1837 2105  
1838 2106  /**
1839 2107   *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1840 2108   *  @hw: pointer to hardware structure
     2109 + *
     2110 + *  Returns a negative error code on error, or the 16-bit checksum
1841 2111   **/
1842      -u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
     2112 +s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1843 2113  {
1844 2114          u16 i;
1845 2115          u16 j;
1846 2116          u16 checksum = 0;
1847 2117          u16 length = 0;
1848 2118          u16 pointer = 0;
1849 2119          u16 word = 0;
1850 2120  
1851 2121          DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1852 2122  
1853 2123          /* Include 0x0-0x3F in the checksum */
1854 2124          for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1855      -                if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
     2125 +                if (hw->eeprom.ops.read(hw, i, &word)) {
1856 2126                          DEBUGOUT("EEPROM read failed\n");
1857      -                        break;
     2127 +                        return IXGBE_ERR_EEPROM;
1858 2128                  }
1859 2129                  checksum += word;
1860 2130          }
1861 2131  
1862 2132          /* Include all data from pointers except for the fw pointer */
1863 2133          for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1864      -                hw->eeprom.ops.read(hw, i, &pointer);
     2134 +                if (hw->eeprom.ops.read(hw, i, &pointer)) {
     2135 +                        DEBUGOUT("EEPROM read failed\n");
     2136 +                        return IXGBE_ERR_EEPROM;
     2137 +                }
1865 2138  
1866      -                /* Make sure the pointer seems valid */
1867      -                if (pointer != 0xFFFF && pointer != 0) {
1868      -                        hw->eeprom.ops.read(hw, pointer, &length);
     2139 +                /* If the pointer seems invalid */
     2140 +                if (pointer == 0xFFFF || pointer == 0)
     2141 +                        continue;
1869 2142  
1870      -                        if (length != 0xFFFF && length != 0) {
1871      -                                for (j = pointer+1; j <= pointer+length; j++) {
1872      -                                        hw->eeprom.ops.read(hw, j, &word);
1873      -                                        checksum += word;
1874      -                                }
     2143 +                if (hw->eeprom.ops.read(hw, pointer, &length)) {
     2144 +                        DEBUGOUT("EEPROM read failed\n");
     2145 +                        return IXGBE_ERR_EEPROM;
     2146 +                }
     2147 +
     2148 +                if (length == 0xFFFF || length == 0)
     2149 +                        continue;
     2150 +
     2151 +                for (j = pointer + 1; j <= pointer + length; j++) {
     2152 +                        if (hw->eeprom.ops.read(hw, j, &word)) {
     2153 +                                DEBUGOUT("EEPROM read failed\n");
     2154 +                                return IXGBE_ERR_EEPROM;
1875 2155                          }
     2156 +                        checksum += word;
1876 2157                  }
1877 2158          }
1878 2159  
1879 2160          checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1880 2161  
1881      -        return checksum;
     2162 +        return (s32)checksum;
1882 2163  }
1883 2164  
1884 2165  /**
1885 2166   *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1886 2167   *  @hw: pointer to hardware structure
1887 2168   *  @checksum_val: calculated checksum
1888 2169   *
1889 2170   *  Performs checksum calculation and validates the EEPROM checksum.  If the
1890 2171   *  caller does not need checksum_val, the value can be NULL.
1891 2172   **/
1892 2173  s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1893 2174                                             u16 *checksum_val)
1894 2175  {
1895 2176          s32 status;
1896 2177          u16 checksum;
1897 2178          u16 read_checksum = 0;
1898 2179  
1899 2180          DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1900 2181  
1901      -        /*
1902      -         * Read the first word from the EEPROM. If this times out or fails, do
     2182 +        /* Read the first word from the EEPROM. If this times out or fails, do
1903 2183           * not continue or we could be in for a very long wait while every
1904 2184           * EEPROM read fails
1905 2185           */
1906 2186          status = hw->eeprom.ops.read(hw, 0, &checksum);
     2187 +        if (status) {
     2188 +                DEBUGOUT("EEPROM read failed\n");
     2189 +                return status;
     2190 +        }
1907 2191  
1908      -        if (status == IXGBE_SUCCESS) {
1909      -                checksum = hw->eeprom.ops.calc_checksum(hw);
     2192 +        status = hw->eeprom.ops.calc_checksum(hw);
     2193 +        if (status < 0)
     2194 +                return status;
1910 2195  
1911      -                hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
     2196 +        checksum = (u16)(status & 0xffff);
1912 2197  
1913      -                /*
1914      -                 * Verify read checksum from EEPROM is the same as
1915      -                 * calculated checksum
1916      -                 */
1917      -                if (read_checksum != checksum)
1918      -                        status = IXGBE_ERR_EEPROM_CHECKSUM;
1919      -
1920      -                /* If the user cares, return the calculated checksum */
1921      -                if (checksum_val)
1922      -                        *checksum_val = checksum;
1923      -        } else {
     2198 +        status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
     2199 +        if (status) {
1924 2200                  DEBUGOUT("EEPROM read failed\n");
     2201 +                return status;
1925 2202          }
1926 2203  
     2204 +        /* Verify read checksum from EEPROM is the same as
     2205 +         * calculated checksum
     2206 +         */
     2207 +        if (read_checksum != checksum)
     2208 +                status = IXGBE_ERR_EEPROM_CHECKSUM;
     2209 +
     2210 +        /* If the user cares, return the calculated checksum */
     2211 +        if (checksum_val)
     2212 +                *checksum_val = checksum;
     2213 +
1927 2214          return status;
1928 2215  }
1929 2216  
1930 2217  /**
1931 2218   *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1932 2219   *  @hw: pointer to hardware structure
1933 2220   **/
1934 2221  s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1935 2222  {
1936 2223          s32 status;
1937 2224          u16 checksum;
1938 2225  
1939 2226          DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1940 2227  
1941      -        /*
1942      -         * Read the first word from the EEPROM. If this times out or fails, do
     2228 +        /* Read the first word from the EEPROM. If this times out or fails, do
1943 2229           * not continue or we could be in for a very long wait while every
1944 2230           * EEPROM read fails
1945 2231           */
1946 2232          status = hw->eeprom.ops.read(hw, 0, &checksum);
1947      -
1948      -        if (status == IXGBE_SUCCESS) {
1949      -                checksum = hw->eeprom.ops.calc_checksum(hw);
1950      -                status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1951      -                                              checksum);
1952      -        } else {
     2233 +        if (status) {
1953 2234                  DEBUGOUT("EEPROM read failed\n");
     2235 +                return status;
1954 2236          }
1955 2237  
     2238 +        status = hw->eeprom.ops.calc_checksum(hw);
     2239 +        if (status < 0)
     2240 +                return status;
     2241 +
     2242 +        checksum = (u16)(status & 0xffff);
     2243 +
     2244 +        status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
     2245 +
1956 2246          return status;
1957 2247  }
1958 2248  
1959 2249  /**
1960 2250   *  ixgbe_validate_mac_addr - Validate MAC address
1961 2251   *  @mac_addr: pointer to MAC address.
1962 2252   *
1963 2253   *  Tests a MAC address to ensure it is a valid Individual Address
1964 2254   **/
1965 2255  s32 ixgbe_validate_mac_addr(u8 *mac_addr)
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1998 2288  s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1999 2289                            u32 enable_addr)
2000 2290  {
2001 2291          u32 rar_low, rar_high;
2002 2292          u32 rar_entries = hw->mac.num_rar_entries;
2003 2293  
2004 2294          DEBUGFUNC("ixgbe_set_rar_generic");
2005 2295  
2006 2296          /* Make sure we are using a valid rar index range */
2007 2297          if (index >= rar_entries) {
2008      -                DEBUGOUT1("RAR index %d is out of range.\n", index);
     2298 +                ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
     2299 +                             "RAR index %d is out of range.\n", index);
2009 2300                  return IXGBE_ERR_INVALID_ARGUMENT;
2010 2301          }
2011 2302  
2012 2303          /* setup VMDq pool selection before this RAR gets enabled */
2013 2304          hw->mac.ops.set_vmdq(hw, index, vmdq);
2014 2305  
2015 2306          /*
2016 2307           * HW expects these in little endian so we reverse the byte
2017 2308           * order from network order (big endian) to little endian
2018 2309           */
↓ open down ↓ 28 lines elided ↑ open up ↑
2047 2338   **/
2048 2339  s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2049 2340  {
2050 2341          u32 rar_high;
2051 2342          u32 rar_entries = hw->mac.num_rar_entries;
2052 2343  
2053 2344          DEBUGFUNC("ixgbe_clear_rar_generic");
2054 2345  
2055 2346          /* Make sure we are using a valid rar index range */
2056 2347          if (index >= rar_entries) {
2057      -                DEBUGOUT1("RAR index %d is out of range.\n", index);
     2348 +                ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
     2349 +                             "RAR index %d is out of range.\n", index);
2058 2350                  return IXGBE_ERR_INVALID_ARGUMENT;
2059 2351          }
2060 2352  
2061 2353          /*
2062 2354           * Some parts put the VMDq setting in the extra RAH bits,
2063 2355           * so save everything except the lower 16 bits that hold part
2064 2356           * of the address and the address valid bit.
2065 2357           */
2066 2358          rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2067 2359          rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
↓ open down ↓ 63 lines elided ↑ open up ↑
2131 2423          }
2132 2424  
2133 2425          /* Clear the MTA */
2134 2426          hw->addr_ctrl.mta_in_use = 0;
2135 2427          IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2136 2428  
2137 2429          DEBUGOUT(" Clearing MTA\n");
2138 2430          for (i = 0; i < hw->mac.mcft_size; i++)
2139 2431                  IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2140 2432  
2141      -        /* Should always be IXGBE_SUCCESS. */
2142      -        return ixgbe_init_uta_tables(hw);
     2433 +        ixgbe_init_uta_tables(hw);
     2434 +
     2435 +        return IXGBE_SUCCESS;
2143 2436  }
2144 2437  
2145 2438  /**
2146 2439   *  ixgbe_add_uc_addr - Adds a secondary unicast address.
2147 2440   *  @hw: pointer to hardware structure
2148 2441   *  @addr: new address
2149 2442   *
2150 2443   *  Adds it to unused receive address register or goes into promiscuous mode.
2151 2444   **/
2152 2445  void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
↓ open down ↓ 191 lines elided ↑ open up ↑
2344 2637          /*
2345 2638           * Set the new number of MC addresses that we are being requested to
2346 2639           * use.
2347 2640           */
2348 2641          hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2349 2642          hw->addr_ctrl.mta_in_use = 0;
2350 2643  
2351 2644          /* Clear mta_shadow */
2352 2645          if (clear) {
2353 2646                  DEBUGOUT(" Clearing MTA\n");
2354      -                (void) memset(&hw->mac.mta_shadow, 0,
2355      -                    sizeof(hw->mac.mta_shadow));
     2647 +                memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2356 2648          }
2357 2649  
2358 2650          /* Update mta_shadow */
2359 2651          for (i = 0; i < mc_addr_count; i++) {
2360 2652                  DEBUGOUT(" Adding the multicast addresses:\n");
2361 2653                  ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2362 2654          }
2363 2655  
2364 2656          /* Enable mta */
2365 2657          for (i = 0; i < hw->mac.mcft_size; i++)
↓ open down ↓ 124 lines elided ↑ open up ↑
2490 2782                   * disabled by software override.
2491 2783                   */
2492 2784                  fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2493 2785                  break;
2494 2786          case ixgbe_fc_full:
2495 2787                  /* Flow control (both Rx and Tx) is enabled by SW override. */
2496 2788                  mflcn_reg |= IXGBE_MFLCN_RFCE;
2497 2789                  fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2498 2790                  break;
2499 2791          default:
2500      -                DEBUGOUT("Flow control param set incorrectly\n");
     2792 +                ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
     2793 +                             "Flow control param set incorrectly\n");
2501 2794                  ret_val = IXGBE_ERR_CONFIG;
2502 2795                  goto out;
     2796 +                break;
2503 2797          }
2504 2798  
2505 2799          /* Set 802.3x based flow control settings. */
2506 2800          mflcn_reg |= IXGBE_MFLCN_DPF;
2507 2801          IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2508 2802          IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2509 2803  
2510 2804  
2511 2805          /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2512 2806          for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2513 2807                  if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2514 2808                      hw->fc.high_water[i]) {
2515 2809                          fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2516 2810                          IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2517 2811                          fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2518 2812                  } else {
2519 2813                          IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2520 2814                          /*
2521 2815                           * In order to prevent Tx hangs when the internal Tx
2522 2816                           * switch is enabled we must set the high water mark
2523      -                         * to the maximum FCRTH value.  This allows the Tx
2524      -                         * switch to function even under heavy Rx workloads.
     2817 +                         * to the Rx packet buffer size - 24KB.  This allows
     2818 +                         * the Tx switch to function even under heavy Rx
     2819 +                         * workloads.
2525 2820                           */
2526      -                        fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
     2821 +                        fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2527 2822                  }
2528 2823  
2529 2824                  IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2530 2825          }
2531 2826  
2532 2827          /* Configure pause time (2 TCs per register) */
2533 2828          reg = hw->fc.pause_time * 0x00010001;
2534 2829          for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2535 2830                  IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2536 2831  
↓ open down ↓ 13 lines elided ↑ open up ↑
2550 2845   *  @adv_asm: asymmetric pause bit in advertisement
2551 2846   *  @lp_sym: symmetric pause bit in link partner advertisement
2552 2847   *  @lp_asm: asymmetric pause bit in link partner advertisement
2553 2848   *
2554 2849   *  Find the intersection between advertised settings and link partner's
2555 2850   *  advertised settings
2556 2851   **/
2557 2852  static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2558 2853                                u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2559 2854  {
2560      -        if ((!(adv_reg)) ||  (!(lp_reg)))
     2855 +        if ((!(adv_reg)) ||  (!(lp_reg))) {
     2856 +                ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
     2857 +                             "Local or link partner's advertised flow control "
     2858 +                             "settings are NULL. Local: %x, link partner: %x\n",
     2859 +                             adv_reg, lp_reg);
2561 2860                  return IXGBE_ERR_FC_NOT_NEGOTIATED;
     2861 +        }
2562 2862  
2563 2863          if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2564 2864                  /*
2565 2865                   * Now we need to check if the user selected Rx ONLY
2566 2866                   * of pause frames.  In this case, we had to advertise
2567 2867                   * FULL flow control because we could not advertise RX
2568 2868                   * ONLY. Hence, we must now check to see if we need to
2569 2869                   * turn OFF the TRANSMISSION of PAUSE frames.
2570 2870                   */
2571 2871                  if (hw->fc.requested_mode == ixgbe_fc_full) {
↓ open down ↓ 30 lines elided ↑ open up ↑
2602 2902          s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2603 2903  
2604 2904          /*
2605 2905           * On multispeed fiber at 1g, bail out if
2606 2906           * - link is up but AN did not complete, or if
2607 2907           * - link is up and AN completed but timed out
2608 2908           */
2609 2909  
2610 2910          linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2611 2911          if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2612      -            (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
     2912 +            (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
     2913 +                DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2613 2914                  goto out;
     2915 +        }
2614 2916  
2615 2917          pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2616 2918          pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2617 2919  
2618 2920          ret_val =  ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2619 2921                                        pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2620 2922                                        IXGBE_PCS1GANA_ASM_PAUSE,
2621 2923                                        IXGBE_PCS1GANA_SYM_PAUSE,
2622 2924                                        IXGBE_PCS1GANA_ASM_PAUSE);
2623 2925  
↓ open down ↓ 11 lines elided ↑ open up ↑
2635 2937  {
2636 2938          u32 links2, anlp1_reg, autoc_reg, links;
2637 2939          s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2638 2940  
2639 2941          /*
2640 2942           * On backplane, bail out if
2641 2943           * - backplane autoneg was not completed, or if
2642 2944           * - we are 82599 and link partner is not AN enabled
2643 2945           */
2644 2946          links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2645      -        if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
     2947 +        if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
     2948 +                DEBUGOUT("Auto-Negotiation did not complete\n");
2646 2949                  goto out;
     2950 +        }
2647 2951  
2648 2952          if (hw->mac.type == ixgbe_mac_82599EB) {
2649 2953                  links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2650      -                if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
     2954 +                if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
     2955 +                        DEBUGOUT("Link partner is not AN enabled\n");
2651 2956                          goto out;
     2957 +                }
2652 2958          }
2653 2959          /*
2654 2960           * Read the 10g AN autoc and LP ability registers and resolve
2655 2961           * local flow control settings accordingly
2656 2962           */
2657 2963          autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2658 2964          anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2659 2965  
2660 2966          ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2661 2967                  anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
↓ open down ↓ 41 lines elided ↑ open up ↑
2703 3009          bool link_up;
2704 3010  
2705 3011          DEBUGFUNC("ixgbe_fc_autoneg");
2706 3012  
2707 3013          /*
2708 3014           * AN should have completed when the cable was plugged in.
2709 3015           * Look for reasons to bail out.  Bail out if:
2710 3016           * - FC autoneg is disabled, or if
2711 3017           * - link is not up.
2712 3018           */
2713      -        if (hw->fc.disable_fc_autoneg)
     3019 +        if (hw->fc.disable_fc_autoneg) {
     3020 +                ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
     3021 +                             "Flow control autoneg is disabled");
2714 3022                  goto out;
     3023 +        }
2715 3024  
2716 3025          hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2717      -        if (!link_up)
     3026 +        if (!link_up) {
     3027 +                ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
2718 3028                  goto out;
     3029 +        }
2719 3030  
2720 3031          switch (hw->phy.media_type) {
2721 3032          /* Autoneg flow control on fiber adapters */
     3033 +        case ixgbe_media_type_fiber_fixed:
     3034 +        case ixgbe_media_type_fiber_qsfp:
2722 3035          case ixgbe_media_type_fiber:
2723 3036                  if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2724 3037                          ret_val = ixgbe_fc_autoneg_fiber(hw);
2725 3038                  break;
2726 3039  
2727 3040          /* Autoneg flow control on backplane adapters */
2728 3041          case ixgbe_media_type_backplane:
2729 3042                  ret_val = ixgbe_fc_autoneg_backplane(hw);
2730 3043                  break;
2731 3044  
2732 3045          /* Autoneg flow control on copper adapters */
2733 3046          case ixgbe_media_type_copper:
2734      -                if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
     3047 +                if (ixgbe_device_supports_autoneg_fc(hw))
2735 3048                          ret_val = ixgbe_fc_autoneg_copper(hw);
2736 3049                  break;
2737 3050  
2738 3051          default:
2739 3052                  break;
2740 3053          }
2741 3054  
2742 3055  out:
2743 3056          if (ret_val == IXGBE_SUCCESS) {
2744 3057                  hw->fc.fc_was_autonegged = TRUE;
2745 3058          } else {
2746 3059                  hw->fc.fc_was_autonegged = FALSE;
2747 3060                  hw->fc.current_mode = hw->fc.requested_mode;
2748 3061          }
2749 3062  }
2750 3063  
     3064 +/*
     3065 + * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
     3066 + * @hw: pointer to hardware structure
     3067 + *
     3068 + * System-wide timeout range is encoded in PCIe Device Control2 register.
     3069 + *
     3070 + * Add 10% to specified maximum and return the number of times to poll for
     3071 + * completion timeout, in units of 100 microsec.  Never return less than
     3072 + * 800 = 80 millisec.
     3073 + */
     3074 +static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
     3075 +{
     3076 +        s16 devctl2;
     3077 +        u32 pollcnt;
     3078 +
     3079 +        devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
     3080 +        devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
     3081 +
     3082 +        switch (devctl2) {
     3083 +        case IXGBE_PCIDEVCTRL2_65_130ms:
     3084 +                pollcnt = 1300;         /* 130 millisec */
     3085 +                break;
     3086 +        case IXGBE_PCIDEVCTRL2_260_520ms:
     3087 +                pollcnt = 5200;         /* 520 millisec */
     3088 +                break;
     3089 +        case IXGBE_PCIDEVCTRL2_1_2s:
     3090 +                pollcnt = 20000;        /* 2 sec */
     3091 +                break;
     3092 +        case IXGBE_PCIDEVCTRL2_4_8s:
     3093 +                pollcnt = 80000;        /* 8 sec */
     3094 +                break;
     3095 +        case IXGBE_PCIDEVCTRL2_17_34s:
     3096 +                pollcnt = 34000;        /* 34 sec */
     3097 +                break;
     3098 +        case IXGBE_PCIDEVCTRL2_50_100us:        /* 100 microsecs */
     3099 +        case IXGBE_PCIDEVCTRL2_1_2ms:           /* 2 millisecs */
     3100 +        case IXGBE_PCIDEVCTRL2_16_32ms:         /* 32 millisec */
     3101 +        case IXGBE_PCIDEVCTRL2_16_32ms_def:     /* 32 millisec default */
     3102 +        default:
     3103 +                pollcnt = 800;          /* 80 millisec minimum */
     3104 +                break;
     3105 +        }
     3106 +
     3107 +        /* add 10% to spec maximum */
     3108 +        return (pollcnt * 11) / 10;
     3109 +}
     3110 +
2751 3111  /**
2752 3112   *  ixgbe_disable_pcie_master - Disable PCI-express master access
2753 3113   *  @hw: pointer to hardware structure
2754 3114   *
2755 3115   *  Disables PCI-Express master access and verifies there are no pending
2756 3116   *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2757 3117   *  bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2758 3118   *  is returned signifying master requests disabled.
2759 3119   **/
2760 3120  s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2761 3121  {
2762 3122          s32 status = IXGBE_SUCCESS;
2763      -        u32 i;
     3123 +        u32 i, poll;
     3124 +        u16 value;
2764 3125  
2765 3126          DEBUGFUNC("ixgbe_disable_pcie_master");
2766 3127  
2767 3128          /* Always set this bit to ensure any future transactions are blocked */
2768 3129          IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2769 3130  
2770      -        /* Exit if master requets are blocked */
2771      -        if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
     3131 +        /* Exit if master requests are blocked */
     3132 +        if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
     3133 +            IXGBE_REMOVED(hw->hw_addr))
2772 3134                  goto out;
2773 3135  
2774 3136          /* Poll for master request bit to clear */
2775 3137          for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2776 3138                  usec_delay(100);
2777 3139                  if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2778 3140                          goto out;
2779 3141          }
2780 3142  
2781 3143          /*
2782 3144           * Two consecutive resets are required via CTRL.RST per datasheet
2783 3145           * 5.2.5.3.2 Master Disable.  We set a flag to inform the reset routine
2784 3146           * of this need.  The first reset prevents new master requests from
2785 3147           * being issued by our device.  We then must wait 1usec or more for any
2786 3148           * remaining completions from the PCIe bus to trickle in, and then reset
2787 3149           * again to clear out any effects they may have had on our device.
2788 3150           */
2789 3151          DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2790 3152          hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2791 3153  
     3154 +        if (hw->mac.type >= ixgbe_mac_X550)
     3155 +                goto out;
     3156 +
2792 3157          /*
2793 3158           * Before proceeding, make sure that the PCIe block does not have
2794 3159           * transactions pending.
2795 3160           */
2796      -        for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
     3161 +        poll = ixgbe_pcie_timeout_poll(hw);
     3162 +        for (i = 0; i < poll; i++) {
2797 3163                  usec_delay(100);
2798      -                if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2799      -                    IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
     3164 +                value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
     3165 +                if (IXGBE_REMOVED(hw->hw_addr))
2800 3166                          goto out;
     3167 +                if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
     3168 +                        goto out;
2801 3169          }
2802 3170  
2803      -        DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
     3171 +        ERROR_REPORT1(IXGBE_ERROR_POLLING,
     3172 +                     "PCIe transaction pending bit also did not clear.\n");
2804 3173          status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2805 3174  
2806 3175  out:
2807 3176          return status;
2808 3177  }
2809 3178  
2810 3179  /**
2811 3180   *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2812 3181   *  @hw: pointer to hardware structure
2813 3182   *  @mask: Mask to specify which semaphore to acquire
2814 3183   *
2815 3184   *  Acquires the SWFW semaphore through the GSSR register for the specified
2816 3185   *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2817 3186   **/
2818      -s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
     3187 +s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2819 3188  {
2820      -        u32 gssr;
     3189 +        u32 gssr = 0;
2821 3190          u32 swmask = mask;
2822 3191          u32 fwmask = mask << 5;
2823      -        s32 timeout = 200;
     3192 +        u32 timeout = 200;
     3193 +        u32 i;
2824 3194  
2825 3195          DEBUGFUNC("ixgbe_acquire_swfw_sync");
2826 3196  
2827      -        while (timeout) {
     3197 +        for (i = 0; i < timeout; i++) {
2828 3198                  /*
2829      -                 * SW EEPROM semaphore bit is used for access to all
2830      -                 * SW_FW_SYNC/GSSR bits (not just EEPROM)
     3199 +                 * SW NVM semaphore bit is used for access to all
     3200 +                 * SW_FW_SYNC bits (not just NVM)
2831 3201                   */
2832 3202                  if (ixgbe_get_eeprom_semaphore(hw))
2833 3203                          return IXGBE_ERR_SWFW_SYNC;
2834 3204  
2835 3205                  gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2836      -                if (!(gssr & (fwmask | swmask)))
2837      -                        break;
2838      -
2839      -                /*
2840      -                 * Firmware currently using resource (fwmask) or other software
2841      -                 * thread currently using resource (swmask)
2842      -                 */
2843      -                ixgbe_release_eeprom_semaphore(hw);
2844      -                msec_delay(5);
2845      -                timeout--;
     3206 +                if (!(gssr & (fwmask | swmask))) {
     3207 +                        gssr |= swmask;
     3208 +                        IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
     3209 +                        ixgbe_release_eeprom_semaphore(hw);
     3210 +                        return IXGBE_SUCCESS;
     3211 +                } else {
     3212 +                        /* Resource is currently in use by FW or SW */
     3213 +                        ixgbe_release_eeprom_semaphore(hw);
     3214 +                        msec_delay(5);
     3215 +                }
2846 3216          }
2847 3217  
2848      -        if (!timeout) {
2849      -                DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2850      -                return IXGBE_ERR_SWFW_SYNC;
2851      -        }
     3218 +        /* If time expired clear the bits holding the lock and retry */
     3219 +        if (gssr & (fwmask | swmask))
     3220 +                ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2852 3221  
2853      -        gssr |= swmask;
2854      -        IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2855      -
2856      -        ixgbe_release_eeprom_semaphore(hw);
2857      -        return IXGBE_SUCCESS;
     3222 +        msec_delay(5);
     3223 +        return IXGBE_ERR_SWFW_SYNC;
2858 3224  }
2859 3225  
2860 3226  /**
2861 3227   *  ixgbe_release_swfw_sync - Release SWFW semaphore
2862 3228   *  @hw: pointer to hardware structure
2863 3229   *  @mask: Mask to specify which semaphore to release
2864 3230   *
2865 3231   *  Releases the SWFW semaphore through the GSSR register for the specified
2866 3232   *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2867 3233   **/
2868      -void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
     3234 +void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2869 3235  {
2870 3236          u32 gssr;
2871 3237          u32 swmask = mask;
2872 3238  
2873 3239          DEBUGFUNC("ixgbe_release_swfw_sync");
2874 3240  
2875      -        (void) ixgbe_get_eeprom_semaphore(hw);
     3241 +        ixgbe_get_eeprom_semaphore(hw);
2876 3242  
2877 3243          gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2878 3244          gssr &= ~swmask;
2879 3245          IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2880 3246  
2881 3247          ixgbe_release_eeprom_semaphore(hw);
2882 3248  }
2883 3249  
2884 3250  /**
2885 3251   *  ixgbe_disable_sec_rx_path_generic - Stops the receive data path
↓ open down ↓ 26 lines elided ↑ open up ↑
2912 3278  
2913 3279          /* For informational purposes only */
2914 3280          if (i >= IXGBE_MAX_SECRX_POLL)
2915 3281                  DEBUGOUT("Rx unit being enabled before security "
2916 3282                           "path fully disabled.  Continuing with init.\n");
2917 3283  
2918 3284          return IXGBE_SUCCESS;
2919 3285  }
2920 3286  
2921 3287  /**
     3288 + *  prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
     3289 + *  @hw: pointer to hardware structure
     3290 + *  @reg_val: Value we read from AUTOC
     3291 + *
     3292 + *  The default case requires no protection so just to the register read.
     3293 + */
     3294 +s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
     3295 +{
     3296 +        *locked = FALSE;
     3297 +        *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
     3298 +        return IXGBE_SUCCESS;
     3299 +}
     3300 +
     3301 +/**
     3302 + * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
     3303 + * @hw: pointer to hardware structure
     3304 + * @reg_val: value to write to AUTOC
     3305 + * @locked: bool to indicate whether the SW/FW lock was already taken by
     3306 + *           previous read.
     3307 + *
     3308 + * The default case requires no protection so just to the register write.
     3309 + */
     3310 +s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
     3311 +{
     3312 +        UNREFERENCED_1PARAMETER(locked);
     3313 +
     3314 +        IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
     3315 +        return IXGBE_SUCCESS;
     3316 +}
     3317 +
     3318 +/**
2922 3319   *  ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2923 3320   *  @hw: pointer to hardware structure
2924 3321   *
2925 3322   *  Enables the receive data path.
2926 3323   **/
2927 3324  s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2928 3325  {
2929 3326          int secrxreg;
2930 3327  
2931 3328          DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
↓ open down ↓ 10 lines elided ↑ open up ↑
2942 3339   *  ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2943 3340   *  @hw: pointer to hardware structure
2944 3341   *  @regval: register value to write to RXCTRL
2945 3342   *
2946 3343   *  Enables the Rx DMA unit
2947 3344   **/
2948 3345  s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2949 3346  {
2950 3347          DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2951 3348  
2952      -        IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
     3349 +        if (regval & IXGBE_RXCTRL_RXEN)
     3350 +                ixgbe_enable_rx(hw);
     3351 +        else
     3352 +                ixgbe_disable_rx(hw);
2953 3353  
2954 3354          return IXGBE_SUCCESS;
2955 3355  }
2956 3356  
2957 3357  /**
2958 3358   *  ixgbe_blink_led_start_generic - Blink LED based on index.
2959 3359   *  @hw: pointer to hardware structure
2960 3360   *  @index: led number to blink
2961 3361   **/
2962 3362  s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2963 3363  {
2964 3364          ixgbe_link_speed speed = 0;
2965 3365          bool link_up = 0;
2966      -        u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
     3366 +        u32 autoc_reg = 0;
2967 3367          u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
     3368 +        s32 ret_val = IXGBE_SUCCESS;
     3369 +        bool locked = FALSE;
2968 3370  
2969 3371          DEBUGFUNC("ixgbe_blink_led_start_generic");
2970 3372  
2971 3373          /*
2972 3374           * Link must be up to auto-blink the LEDs;
2973 3375           * Force it if link is down.
2974 3376           */
2975 3377          hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2976 3378  
2977 3379          if (!link_up) {
     3380 +                ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
     3381 +                if (ret_val != IXGBE_SUCCESS)
     3382 +                        goto out;
     3383 +
2978 3384                  autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979 3385                  autoc_reg |= IXGBE_AUTOC_FLU;
2980      -                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
     3386 +
     3387 +                ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
     3388 +                if (ret_val != IXGBE_SUCCESS)
     3389 +                        goto out;
     3390 +
2981 3391                  IXGBE_WRITE_FLUSH(hw);
2982 3392                  msec_delay(10);
2983 3393          }
2984 3394  
2985 3395          led_reg &= ~IXGBE_LED_MODE_MASK(index);
2986 3396          led_reg |= IXGBE_LED_BLINK(index);
2987 3397          IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988 3398          IXGBE_WRITE_FLUSH(hw);
2989 3399  
2990      -        return IXGBE_SUCCESS;
     3400 +out:
     3401 +        return ret_val;
2991 3402  }
2992 3403  
2993 3404  /**
2994 3405   *  ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2995 3406   *  @hw: pointer to hardware structure
2996 3407   *  @index: led number to stop blinking
2997 3408   **/
2998 3409  s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2999 3410  {
3000      -        u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
     3411 +        u32 autoc_reg = 0;
3001 3412          u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
     3413 +        s32 ret_val = IXGBE_SUCCESS;
     3414 +        bool locked = FALSE;
3002 3415  
3003 3416          DEBUGFUNC("ixgbe_blink_led_stop_generic");
3004 3417  
     3418 +        ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
     3419 +        if (ret_val != IXGBE_SUCCESS)
     3420 +                goto out;
3005 3421  
3006 3422          autoc_reg &= ~IXGBE_AUTOC_FLU;
3007 3423          autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008      -        IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3009 3424  
     3425 +        ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
     3426 +        if (ret_val != IXGBE_SUCCESS)
     3427 +                goto out;
     3428 +
3010 3429          led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011 3430          led_reg &= ~IXGBE_LED_BLINK(index);
3012 3431          led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013 3432          IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014 3433          IXGBE_WRITE_FLUSH(hw);
3015 3434  
3016      -        return IXGBE_SUCCESS;
     3435 +out:
     3436 +        return ret_val;
3017 3437  }
3018 3438  
3019 3439  /**
3020 3440   *  ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3021 3441   *  @hw: pointer to hardware structure
3022 3442   *  @san_mac_offset: SAN MAC address offset
3023 3443   *
3024 3444   *  This function will read the EEPROM location for the SAN MAC address
3025 3445   *  pointer, and returns the value at that location.  This is used in both
3026 3446   *  get and set mac_addr routines.
3027 3447   **/
3028 3448  static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3029 3449                                           u16 *san_mac_offset)
3030 3450  {
     3451 +        s32 ret_val;
     3452 +
3031 3453          DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3032 3454  
3033 3455          /*
3034 3456           * First read the EEPROM pointer to see if the MAC addresses are
3035 3457           * available.
3036 3458           */
3037      -        hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
     3459 +        ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
     3460 +                                      san_mac_offset);
     3461 +        if (ret_val) {
     3462 +                ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
     3463 +                              "eeprom at offset %d failed",
     3464 +                              IXGBE_SAN_MAC_ADDR_PTR);
     3465 +        }
3038 3466  
3039      -        return IXGBE_SUCCESS;
     3467 +        return ret_val;
3040 3468  }
3041 3469  
3042 3470  /**
3043 3471   *  ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3044 3472   *  @hw: pointer to hardware structure
3045 3473   *  @san_mac_addr: SAN MAC address
3046 3474   *
3047 3475   *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
3048 3476   *  per-port, so set_lan_id() must be called before reading the addresses.
3049 3477   *  set_lan_id() is called by identify_sfp(), but this cannot be relied
3050 3478   *  upon for non-SFP connections, so we must call it here.
3051 3479   **/
3052 3480  s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3053 3481  {
3054 3482          u16 san_mac_data, san_mac_offset;
3055 3483          u8 i;
     3484 +        s32 ret_val;
3056 3485  
3057 3486          DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3058 3487  
3059 3488          /*
3060 3489           * First read the EEPROM pointer to see if the MAC addresses are
3061 3490           * available.  If they're not, no point in calling set_lan_id() here.
3062 3491           */
3063      -        (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3064      -
3065      -        if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3066      -                /*
3067      -                 * No addresses available in this EEPROM.  It's not an
3068      -                 * error though, so just wipe the local address and return.
3069      -                 */
3070      -                for (i = 0; i < 6; i++)
3071      -                        san_mac_addr[i] = 0xFF;
3072      -
     3492 +        ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
     3493 +        if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3073 3494                  goto san_mac_addr_out;
3074      -        }
3075 3495  
3076 3496          /* make sure we know which port we need to program */
3077 3497          hw->mac.ops.set_lan_id(hw);
3078 3498          /* apply the port offset to the address offset */
3079 3499          (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3080 3500                           (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3081 3501          for (i = 0; i < 3; i++) {
3082      -                hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
     3502 +                ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
     3503 +                                              &san_mac_data);
     3504 +                if (ret_val) {
     3505 +                        ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
     3506 +                                      "eeprom read at offset %d failed",
     3507 +                                      san_mac_offset);
     3508 +                        goto san_mac_addr_out;
     3509 +                }
3083 3510                  san_mac_addr[i * 2] = (u8)(san_mac_data);
3084 3511                  san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3085 3512                  san_mac_offset++;
3086 3513          }
     3514 +        return IXGBE_SUCCESS;
3087 3515  
3088 3516  san_mac_addr_out:
     3517 +        /*
     3518 +         * No addresses available in this EEPROM.  It's not an
     3519 +         * error though, so just wipe the local address and return.
     3520 +         */
     3521 +        for (i = 0; i < 6; i++)
     3522 +                san_mac_addr[i] = 0xFF;
3089 3523          return IXGBE_SUCCESS;
3090 3524  }
3091 3525  
3092 3526  /**
3093 3527   *  ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3094 3528   *  @hw: pointer to hardware structure
3095 3529   *  @san_mac_addr: SAN MAC address
3096 3530   *
3097 3531   *  Write a SAN MAC address to the EEPROM.
3098 3532   **/
3099 3533  s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3100 3534  {
3101      -        s32 status = IXGBE_SUCCESS;
     3535 +        s32 ret_val;
3102 3536          u16 san_mac_data, san_mac_offset;
3103 3537          u8 i;
3104 3538  
3105 3539          DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3106 3540  
3107 3541          /* Look for SAN mac address pointer.  If not defined, return */
3108      -        (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
     3542 +        ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
     3543 +        if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
     3544 +                return IXGBE_ERR_NO_SAN_ADDR_PTR;
3109 3545  
3110      -        if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3111      -                status = IXGBE_ERR_NO_SAN_ADDR_PTR;
3112      -                goto san_mac_addr_out;
3113      -        }
3114      -
3115 3546          /* Make sure we know which port we need to write */
3116 3547          hw->mac.ops.set_lan_id(hw);
3117 3548          /* Apply the port offset to the address offset */
3118 3549          (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3119 3550                           (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3120 3551  
3121 3552          for (i = 0; i < 3; i++) {
3122 3553                  san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3123 3554                  san_mac_data |= (u16)(san_mac_addr[i * 2]);
3124 3555                  hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3125 3556                  san_mac_offset++;
3126 3557          }
3127 3558  
3128      -san_mac_addr_out:
3129      -        return status;
     3559 +        return IXGBE_SUCCESS;
3130 3560  }
3131 3561  
3132 3562  /**
3133 3563   *  ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3134 3564   *  @hw: pointer to hardware structure
3135 3565   *
3136 3566   *  Read PCIe configuration space, and get the MSI-X vector count from
3137 3567   *  the capabilities table.
3138 3568   **/
3139 3569  u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
↓ open down ↓ 2 lines elided ↑ open up ↑
3142 3572          u16 max_msix_count;
3143 3573          u16 pcie_offset;
3144 3574  
3145 3575          switch (hw->mac.type) {
3146 3576          case ixgbe_mac_82598EB:
3147 3577                  pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3148 3578                  max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3149 3579                  break;
3150 3580          case ixgbe_mac_82599EB:
3151 3581          case ixgbe_mac_X540:
     3582 +        case ixgbe_mac_X550:
     3583 +        case ixgbe_mac_X550EM_x:
3152 3584                  pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3153 3585                  max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3154 3586                  break;
3155 3587          default:
3156 3588                  return msix_count;
3157 3589          }
3158 3590  
3159 3591          DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3160 3592          msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
     3593 +        if (IXGBE_REMOVED(hw->hw_addr))
     3594 +                msix_count = 0;
3161 3595          msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3162 3596  
3163 3597          /* MSI-X count is zero-based in HW */
3164 3598          msix_count++;
3165 3599  
3166 3600          if (msix_count > max_msix_count)
3167 3601                  msix_count = max_msix_count;
3168 3602  
3169 3603          return msix_count;
3170 3604  }
3171 3605  
3172 3606  /**
3173 3607   *  ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3174 3608   *  @hw: pointer to hardware structure
3175 3609   *  @addr: Address to put into receive address register
3176 3610   *  @vmdq: VMDq pool to assign
3177 3611   *
3178 3612   *  Puts an ethernet address into a receive address register, or
3179      - *  finds the rar that it is aleady in; adds to the pool list
     3613 + *  finds the rar that it is already in; adds to the pool list
3180 3614   **/
3181 3615  s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3182 3616  {
3183 3617          static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3184 3618          u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3185 3619          u32 rar;
3186 3620          u32 rar_low, rar_high;
3187 3621          u32 addr_low, addr_high;
3188 3622  
3189 3623          DEBUGFUNC("ixgbe_insert_mac_addr_generic");
↓ open down ↓ 18 lines elided ↑ open up ↑
3208 3642                          first_empty_rar = rar;
3209 3643                  } else if ((rar_high & 0xFFFF) == addr_high) {
3210 3644                          rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3211 3645                          if (rar_low == addr_low)
3212 3646                                  break;    /* found it already in the rars */
3213 3647                  }
3214 3648          }
3215 3649  
3216 3650          if (rar < hw->mac.rar_highwater) {
3217 3651                  /* already there so just add to the pool bits */
3218      -                (void) ixgbe_set_vmdq(hw, rar, vmdq);
     3652 +                ixgbe_set_vmdq(hw, rar, vmdq);
3219 3653          } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3220 3654                  /* stick it into first empty RAR slot we found */
3221 3655                  rar = first_empty_rar;
3222      -                (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
     3656 +                ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3223 3657          } else if (rar == hw->mac.rar_highwater) {
3224 3658                  /* add it to the top of the list and inc the highwater mark */
3225      -                (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
     3659 +                ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3226 3660                  hw->mac.rar_highwater++;
3227 3661          } else if (rar >= hw->mac.num_rar_entries) {
3228 3662                  return IXGBE_ERR_INVALID_MAC_ADDR;
3229 3663          }
3230 3664  
3231 3665          /*
3232 3666           * If we found rar[0], make sure the default pool bit (we use pool 0)
3233 3667           * remains cleared to be sure default pool packets will get delivered
3234 3668           */
3235 3669          if (rar == 0)
3236      -                (void) ixgbe_clear_vmdq(hw, rar, 0);
     3670 +                ixgbe_clear_vmdq(hw, rar, 0);
3237 3671  
3238 3672          return rar;
3239 3673  }
3240 3674  
3241 3675  /**
3242 3676   *  ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3243 3677   *  @hw: pointer to hardware struct
3244 3678   *  @rar: receive address register index to disassociate
3245 3679   *  @vmdq: VMDq pool index to remove from the rar
3246 3680   **/
3247 3681  s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3248 3682  {
3249 3683          u32 mpsar_lo, mpsar_hi;
3250 3684          u32 rar_entries = hw->mac.num_rar_entries;
3251 3685  
3252 3686          DEBUGFUNC("ixgbe_clear_vmdq_generic");
3253 3687  
3254 3688          /* Make sure we are using a valid rar index range */
3255 3689          if (rar >= rar_entries) {
3256      -                DEBUGOUT1("RAR index %d is out of range.\n", rar);
     3690 +                ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
     3691 +                             "RAR index %d is out of range.\n", rar);
3257 3692                  return IXGBE_ERR_INVALID_ARGUMENT;
3258 3693          }
3259 3694  
3260 3695          mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3261 3696          mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3262 3697  
     3698 +        if (IXGBE_REMOVED(hw->hw_addr))
     3699 +                goto done;
     3700 +
3263 3701          if (!mpsar_lo && !mpsar_hi)
3264 3702                  goto done;
3265 3703  
3266 3704          if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3267 3705                  if (mpsar_lo) {
3268 3706                          IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3269 3707                          mpsar_lo = 0;
3270 3708                  }
3271 3709                  if (mpsar_hi) {
3272 3710                          IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
↓ open down ↓ 22 lines elided ↑ open up ↑
3295 3733   **/
3296 3734  s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3297 3735  {
3298 3736          u32 mpsar;
3299 3737          u32 rar_entries = hw->mac.num_rar_entries;
3300 3738  
3301 3739          DEBUGFUNC("ixgbe_set_vmdq_generic");
3302 3740  
3303 3741          /* Make sure we are using a valid rar index range */
3304 3742          if (rar >= rar_entries) {
3305      -                DEBUGOUT1("RAR index %d is out of range.\n", rar);
     3743 +                ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
     3744 +                             "RAR index %d is out of range.\n", rar);
3306 3745                  return IXGBE_ERR_INVALID_ARGUMENT;
3307 3746          }
3308 3747  
3309 3748          if (vmdq < 32) {
3310 3749                  mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3311 3750                  mpsar |= 1 << vmdq;
3312 3751                  IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3313 3752          } else {
3314 3753                  mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3315 3754                  mpsar |= 1 << (vmdq - 32);
↓ open down ↓ 78 lines elided ↑ open up ↑
3394 3833  
3395 3834          /*
3396 3835            * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3397 3836            * in the VLVF. Else use the first empty VLVF register for this
3398 3837            * vlan id.
3399 3838            */
3400 3839          if (regindex >= IXGBE_VLVF_ENTRIES) {
3401 3840                  if (first_empty_slot)
3402 3841                          regindex = first_empty_slot;
3403 3842                  else {
3404      -                        DEBUGOUT("No space in VLVF.\n");
     3843 +                        ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
     3844 +                                     "No space in VLVF.\n");
3405 3845                          regindex = IXGBE_ERR_NO_SPACE;
3406 3846                  }
3407 3847          }
3408 3848  
3409 3849          return regindex;
3410 3850  }
3411 3851  
3412 3852  /**
3413 3853   *  ixgbe_set_vfta_generic - Set VLAN filter table
3414 3854   *  @hw: pointer to hardware structure
↓ open down ↓ 214 lines elided ↑ open up ↑
3629 4069          links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3630 4070  
3631 4071          links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3632 4072  
3633 4073          if (links_orig != links_reg) {
3634 4074                  DEBUGOUT2("LINKS changed from %08X to %08X\n",
3635 4075                            links_orig, links_reg);
3636 4076          }
3637 4077  
3638 4078          if (link_up_wait_to_complete) {
3639      -                for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
     4079 +                for (i = 0; i < hw->mac.max_link_up_time; i++) {
3640 4080                          if (links_reg & IXGBE_LINKS_UP) {
3641 4081                                  *link_up = TRUE;
3642 4082                                  break;
3643 4083                          } else {
3644 4084                                  *link_up = FALSE;
3645 4085                          }
3646 4086                          msec_delay(100);
3647 4087                          links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3648 4088                  }
3649 4089          } else {
3650 4090                  if (links_reg & IXGBE_LINKS_UP)
3651 4091                          *link_up = TRUE;
3652 4092                  else
3653 4093                          *link_up = FALSE;
3654 4094          }
3655 4095  
3656      -        if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3657      -            IXGBE_LINKS_SPEED_10G_82599)
     4096 +        switch (links_reg & IXGBE_LINKS_SPEED_82599) {
     4097 +        case IXGBE_LINKS_SPEED_10G_82599:
3658 4098                  *speed = IXGBE_LINK_SPEED_10GB_FULL;
3659      -        else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3660      -                 IXGBE_LINKS_SPEED_1G_82599)
     4099 +                if (hw->mac.type >= ixgbe_mac_X550) {
     4100 +                        if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
     4101 +                                *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
     4102 +                }
     4103 +                break;
     4104 +        case IXGBE_LINKS_SPEED_1G_82599:
3661 4105                  *speed = IXGBE_LINK_SPEED_1GB_FULL;
3662      -        else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3663      -                 IXGBE_LINKS_SPEED_100_82599)
     4106 +                break;
     4107 +        case IXGBE_LINKS_SPEED_100_82599:
3664 4108                  *speed = IXGBE_LINK_SPEED_100_FULL;
3665      -        else
     4109 +                if (hw->mac.type >= ixgbe_mac_X550) {
     4110 +                        if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
     4111 +                                *speed = IXGBE_LINK_SPEED_5GB_FULL;
     4112 +                }
     4113 +                break;
     4114 +        default:
3666 4115                  *speed = IXGBE_LINK_SPEED_UNKNOWN;
     4116 +        }
3667 4117  
3668 4118          return IXGBE_SUCCESS;
3669 4119  }
3670 4120  
3671 4121  /**
3672 4122   *  ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3673 4123   *  the EEPROM
3674 4124   *  @hw: pointer to hardware structure
3675 4125   *  @wwnn_prefix: the alternative WWNN prefix
3676 4126   *  @wwpn_prefix: the alternative WWPN prefix
↓ open down ↓ 7 lines elided ↑ open up ↑
3684 4134          u16 offset, caps;
3685 4135          u16 alt_san_mac_blk_offset;
3686 4136  
3687 4137          DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3688 4138  
3689 4139          /* clear output first */
3690 4140          *wwnn_prefix = 0xFFFF;
3691 4141          *wwpn_prefix = 0xFFFF;
3692 4142  
3693 4143          /* check if alternative SAN MAC is supported */
3694      -        hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3695      -                            &alt_san_mac_blk_offset);
     4144 +        offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
     4145 +        if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
     4146 +                goto wwn_prefix_err;
3696 4147  
3697 4148          if ((alt_san_mac_blk_offset == 0) ||
3698 4149              (alt_san_mac_blk_offset == 0xFFFF))
3699 4150                  goto wwn_prefix_out;
3700 4151  
3701 4152          /* check capability in alternative san mac address block */
3702 4153          offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3703      -        hw->eeprom.ops.read(hw, offset, &caps);
     4154 +        if (hw->eeprom.ops.read(hw, offset, &caps))
     4155 +                goto wwn_prefix_err;
3704 4156          if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3705 4157                  goto wwn_prefix_out;
3706 4158  
3707 4159          /* get the corresponding prefix for WWNN/WWPN */
3708 4160          offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3709      -        hw->eeprom.ops.read(hw, offset, wwnn_prefix);
     4161 +        if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
     4162 +                ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
     4163 +                              "eeprom read at offset %d failed", offset);
     4164 +        }
3710 4165  
3711 4166          offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3712      -        hw->eeprom.ops.read(hw, offset, wwpn_prefix);
     4167 +        if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
     4168 +                goto wwn_prefix_err;
3713 4169  
3714 4170  wwn_prefix_out:
3715 4171          return IXGBE_SUCCESS;
     4172 +
     4173 +wwn_prefix_err:
     4174 +        ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
     4175 +                      "eeprom read at offset %d failed", offset);
     4176 +        return IXGBE_SUCCESS;
3716 4177  }
3717 4178  
3718 4179  /**
3719 4180   *  ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3720 4181   *  @hw: pointer to hardware structure
3721 4182   *  @bs: the fcoe boot status
3722 4183   *
3723 4184   *  This function will read the FCOE boot status from the iSCSI FCOE block
3724 4185   **/
3725 4186  s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
↓ open down ↓ 77 lines elided ↑ open up ↑
3803 4264           * anti-spoofing enabled.
3804 4265           */
3805 4266          for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3806 4267                  IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3807 4268  }
3808 4269  
3809 4270  /**
3810 4271   *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3811 4272   *  @hw: pointer to hardware structure
3812 4273   *  @enable: enable or disable switch for VLAN anti-spoofing
3813      - *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
     4274 + *  @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3814 4275   *
3815 4276   **/
3816 4277  void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3817 4278  {
3818 4279          int vf_target_reg = vf >> 3;
3819 4280          int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3820 4281          u32 pfvfspoof;
3821 4282  
3822 4283          if (hw->mac.type == ixgbe_mac_82598EB)
3823 4284                  return;
↓ open down ↓ 51 lines elided ↑ open up ↑
3875 4336  
3876 4337  }
3877 4338  
3878 4339  /**
3879 4340   *  ixgbe_calculate_checksum - Calculate checksum for buffer
3880 4341   *  @buffer: pointer to EEPROM
3881 4342   *  @length: size of EEPROM to calculate a checksum for
3882 4343   *  Calculates the checksum for some buffer on a specified length.  The
3883 4344   *  checksum calculated is returned.
3884 4345   **/
3885      -static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
     4346 +u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3886 4347  {
3887 4348          u32 i;
3888 4349          u8 sum = 0;
3889 4350  
3890 4351          DEBUGFUNC("ixgbe_calculate_checksum");
3891 4352  
3892 4353          if (!buffer)
3893 4354                  return 0;
3894 4355  
3895 4356          for (i = 0; i < length; i++)
↓ open down ↓ 1 lines elided ↑ open up ↑
3897 4358  
3898 4359          return (u8) (0 - sum);
3899 4360  }
3900 4361  
3901 4362  /**
3902 4363   *  ixgbe_host_interface_command - Issue command to manageability block
3903 4364   *  @hw: pointer to the HW structure
3904 4365   *  @buffer: contains the command to write and where the return status will
3905 4366   *   be placed
3906 4367   *  @length: length of buffer, must be multiple of 4 bytes
     4368 + *  @timeout: time in ms to wait for command completion
     4369 + *  @return_data: read and return data from the buffer (TRUE) or not (FALSE)
     4370 + *   Needed because FW structures are big endian and decoding of
     4371 + *   these fields can be 8 bit or 16 bit based on command. Decoding
     4372 + *   is not easily understood without making a table of commands.
     4373 + *   So we will leave this up to the caller to read back the data
     4374 + *   in these cases.
3907 4375   *
3908 4376   *  Communicates with the manageability block.  On success return IXGBE_SUCCESS
3909 4377   *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3910 4378   **/
3911      -static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3912      -                                        u32 length)
     4379 +s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
     4380 +                                 u32 length, u32 timeout, bool return_data)
3913 4381  {
3914      -        u32 hicr, i, bi;
     4382 +        u32 hicr, i, bi, fwsts;
3915 4383          u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3916      -        u8 buf_len, dword_len;
     4384 +        u16 buf_len;
     4385 +        u16 dword_len;
3917 4386  
3918      -        s32 ret_val = IXGBE_SUCCESS;
3919      -
3920 4387          DEBUGFUNC("ixgbe_host_interface_command");
3921 4388  
3922      -        if (length == 0 || length & 0x3 ||
3923      -            length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3924      -                DEBUGOUT("Buffer length failure.\n");
3925      -                ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3926      -                goto out;
     4389 +        if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
     4390 +                DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
     4391 +                return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3927 4392          }
     4393 +        /* Set bit 9 of FWSTS clearing FW reset indication */
     4394 +        fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
     4395 +        IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3928 4396  
3929 4397          /* Check that the host interface is enabled. */
3930 4398          hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3931 4399          if ((hicr & IXGBE_HICR_EN) == 0) {
3932 4400                  DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
3933      -                ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3934      -                goto out;
     4401 +                return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3935 4402          }
3936 4403  
3937      -        /* Calculate length in DWORDs */
     4404 +        /* Calculate length in DWORDs. We must be DWORD aligned */
     4405 +        if ((length % (sizeof(u32))) != 0) {
     4406 +                DEBUGOUT("Buffer length failure, not aligned to dword");
     4407 +                return IXGBE_ERR_INVALID_ARGUMENT;
     4408 +        }
     4409 +
3938 4410          dword_len = length >> 2;
3939 4411  
3940      -        /*
3941      -         * The device driver writes the relevant command block
     4412 +        /* The device driver writes the relevant command block
3942 4413           * into the ram area.
3943 4414           */
3944 4415          for (i = 0; i < dword_len; i++)
3945 4416                  IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3946 4417                                        i, IXGBE_CPU_TO_LE32(buffer[i]));
3947 4418  
3948 4419          /* Setting this bit tells the ARC that a new command is pending. */
3949 4420          IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3950 4421  
3951      -        for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
     4422 +        for (i = 0; i < timeout; i++) {
3952 4423                  hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3953 4424                  if (!(hicr & IXGBE_HICR_C))
3954 4425                          break;
3955 4426                  msec_delay(1);
3956 4427          }
3957 4428  
3958      -        /* Check command successful completion. */
3959      -        if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3960      -            (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3961      -                DEBUGOUT("Command has failed with no status valid.\n");
3962      -                ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3963      -                goto out;
     4429 +        /* Check command completion */
     4430 +        if ((timeout != 0 && i == timeout) ||
     4431 +            !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
     4432 +                ERROR_REPORT1(IXGBE_ERROR_CAUTION,
     4433 +                             "Command has failed with no status valid.\n");
     4434 +                return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3964 4435          }
3965 4436  
     4437 +        if (!return_data)
     4438 +                return 0;
     4439 +
3966 4440          /* Calculate length in DWORDs */
3967 4441          dword_len = hdr_size >> 2;
3968 4442  
3969 4443          /* first pull in the header so we know the buffer length */
3970 4444          for (bi = 0; bi < dword_len; bi++) {
3971 4445                  buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3972      -                buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
     4446 +                IXGBE_LE32_TO_CPUS(&buffer[bi]);
3973 4447          }
3974 4448  
3975 4449          /* If there is any thing in data position pull it in */
3976 4450          buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3977 4451          if (buf_len == 0)
3978      -                goto out;
     4452 +                return 0;
3979 4453  
3980      -        if (length < (buf_len + hdr_size)) {
     4454 +        if (length < buf_len + hdr_size) {
3981 4455                  DEBUGOUT("Buffer not large enough for reply message.\n");
3982      -                ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3983      -                goto out;
     4456 +                return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3984 4457          }
3985 4458  
3986 4459          /* Calculate length in DWORDs, add 3 for odd lengths */
3987 4460          dword_len = (buf_len + 3) >> 2;
3988 4461  
3989      -        /* Pull in the rest of the buffer (bi is where we left off)*/
     4462 +        /* Pull in the rest of the buffer (bi is where we left off) */
3990 4463          for (; bi <= dword_len; bi++) {
3991 4464                  buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3992      -                buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
     4465 +                IXGBE_LE32_TO_CPUS(&buffer[bi]);
3993 4466          }
3994 4467  
3995      -out:
3996      -        return ret_val;
     4468 +        return 0;
3997 4469  }
3998 4470  
3999 4471  /**
4000 4472   *  ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4001 4473   *  @hw: pointer to the HW structure
4002 4474   *  @maj: driver version major number
4003 4475   *  @min: driver version minor number
4004 4476   *  @build: driver version build number
4005 4477   *  @sub: driver version sub build number
4006 4478   *
↓ open down ↓ 25 lines elided ↑ open up ↑
4032 4504          fw_cmd.ver_min = min;
4033 4505          fw_cmd.ver_build = build;
4034 4506          fw_cmd.ver_sub = sub;
4035 4507          fw_cmd.hdr.checksum = 0;
4036 4508          fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4037 4509                                  (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4038 4510          fw_cmd.pad = 0;
4039 4511          fw_cmd.pad2 = 0;
4040 4512  
4041 4513          for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4042      -                /* LINTED */
4043 4514                  ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4044      -                                                       sizeof(fw_cmd));
     4515 +                                                       sizeof(fw_cmd),
     4516 +                                                       IXGBE_HI_COMMAND_TIMEOUT,
     4517 +                                                       TRUE);
4045 4518                  if (ret_val != IXGBE_SUCCESS)
4046 4519                          continue;
4047 4520  
4048 4521                  if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4049 4522                      FW_CEM_RESP_STATUS_SUCCESS)
4050 4523                          ret_val = IXGBE_SUCCESS;
4051 4524                  else
4052 4525                          ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4053 4526  
4054 4527                  break;
↓ open down ↓ 31 lines elided ↑ open up ↑
4086 4559          case PBA_STRATEGY_WEIGHTED:
4087 4560                  /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4088 4561                   * buffer with 5/8 of the packet buffer space.
4089 4562                   */
4090 4563                  rxpktsize = (pbsize * 5) / (num_pb * 4);
4091 4564                  pbsize -= rxpktsize * (num_pb / 2);
4092 4565                  rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4093 4566                  for (; i < (num_pb / 2); i++)
4094 4567                          IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4095 4568                  /* Fall through to configure remaining packet buffers */
4096      -                /* FALLTHRU */
4097 4569          case PBA_STRATEGY_EQUAL:
4098 4570                  rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4099 4571                  for (; i < num_pb; i++)
4100 4572                          IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4101 4573                  break;
4102 4574          default:
4103 4575                  break;
4104 4576          }
4105 4577  
4106 4578          /* Only support an equally distributed Tx packet buffer strategy. */
↓ open down ↓ 15 lines elided ↑ open up ↑
4122 4594  /**
4123 4595   * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4124 4596   * @hw: pointer to the hardware structure
4125 4597   *
4126 4598   * The 82599 and x540 MACs can experience issues if TX work is still pending
4127 4599   * when a reset occurs.  This function prevents this by flushing the PCIe
4128 4600   * buffers on the system.
4129 4601   **/
4130 4602  void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4131 4603  {
4132      -        u32 gcr_ext, hlreg0;
     4604 +        u32 gcr_ext, hlreg0, i, poll;
     4605 +        u16 value;
4133 4606  
4134 4607          /*
4135 4608           * If double reset is not requested then all transactions should
4136 4609           * already be clear and as such there is no work to do
4137 4610           */
4138 4611          if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4139 4612                  return;
4140 4613  
4141 4614          /*
4142 4615           * Set loopback enable to prevent any transmits from being sent
4143 4616           * should the link come up.  This assumes that the RXCTRL.RXEN bit
4144 4617           * has already been cleared.
4145 4618           */
4146 4619          hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4147 4620          IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4148 4621  
     4622 +        /* Wait for a last completion before clearing buffers */
     4623 +        IXGBE_WRITE_FLUSH(hw);
     4624 +        msec_delay(3);
     4625 +
     4626 +        /*
     4627 +         * Before proceeding, make sure that the PCIe block does not have
     4628 +         * transactions pending.
     4629 +         */
     4630 +        poll = ixgbe_pcie_timeout_poll(hw);
     4631 +        for (i = 0; i < poll; i++) {
     4632 +                usec_delay(100);
     4633 +                value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
     4634 +                if (IXGBE_REMOVED(hw->hw_addr))
     4635 +                        goto out;
     4636 +                if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
     4637 +                        goto out;
     4638 +        }
     4639 +
     4640 +out:
4149 4641          /* initiate cleaning flow for buffers in the PCIe transaction layer */
4150 4642          gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4151 4643          IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4152 4644                          gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4153 4645  
4154 4646          /* Flush all writes and allow 20usec for all transactions to clear */
4155 4647          IXGBE_WRITE_FLUSH(hw);
4156 4648          usec_delay(20);
4157 4649  
4158 4650          /* restore previous register values */
4159 4651          IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4160 4652          IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4161 4653  }
4162 4654  
     4655 +
     4656 +/**
     4657 + * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
     4658 + * @hw: pointer to hardware structure
     4659 + * @map: pointer to u8 arr for returning map
     4660 + *
     4661 + * Read the rtrup2tc HW register and resolve its content into map
     4662 + **/
     4663 +void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
     4664 +{
     4665 +        u32 reg, i;
     4666 +
     4667 +        reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
     4668 +        for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
     4669 +                map[i] = IXGBE_RTRUP2TC_UP_MASK &
     4670 +                        (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
     4671 +        return;
     4672 +}
     4673 +
     4674 +void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
     4675 +{
     4676 +        u32 pfdtxgswc;
     4677 +        u32 rxctrl;
     4678 +
     4679 +        rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
     4680 +        if (rxctrl & IXGBE_RXCTRL_RXEN) {
     4681 +                if (hw->mac.type != ixgbe_mac_82598EB) {
     4682 +                        pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
     4683 +                        if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
     4684 +                                pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
     4685 +                                IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
     4686 +                                hw->mac.set_lben = TRUE;
     4687 +                        } else {
     4688 +                                hw->mac.set_lben = FALSE;
     4689 +                        }
     4690 +                }
     4691 +                rxctrl &= ~IXGBE_RXCTRL_RXEN;
     4692 +                IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
     4693 +        }
     4694 +}
     4695 +
     4696 +void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
     4697 +{
     4698 +        u32 pfdtxgswc;
     4699 +        u32 rxctrl;
     4700 +
     4701 +        rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
     4702 +        IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
     4703 +
     4704 +        if (hw->mac.type != ixgbe_mac_82598EB) {
     4705 +                if (hw->mac.set_lben) {
     4706 +                        pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
     4707 +                        pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
     4708 +                        IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
     4709 +                        hw->mac.set_lben = FALSE;
     4710 +                }
     4711 +        }
     4712 +}
     4713 +
     4714 +/**
     4715 + * ixgbe_mng_present - returns TRUE when management capability is present
     4716 + * @hw: pointer to hardware structure
     4717 + */
     4718 +bool ixgbe_mng_present(struct ixgbe_hw *hw)
     4719 +{
     4720 +        u32 fwsm;
     4721 +
     4722 +        if (hw->mac.type < ixgbe_mac_82599EB)
     4723 +                return FALSE;
     4724 +
     4725 +        fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
     4726 +        fwsm &= IXGBE_FWSM_MODE_MASK;
     4727 +        return fwsm == IXGBE_FWSM_FW_MODE_PT;
     4728 +}
     4729 +
     4730 +/**
     4731 + * ixgbe_mng_enabled - Is the manageability engine enabled?
     4732 + * @hw: pointer to hardware structure
     4733 + *
     4734 + * Returns TRUE if the manageability engine is enabled.
     4735 + **/
     4736 +bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
     4737 +{
     4738 +        u32 fwsm, manc, factps;
     4739 +
     4740 +        fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
     4741 +        if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
     4742 +                return FALSE;
     4743 +
     4744 +        manc = IXGBE_READ_REG(hw, IXGBE_MANC);
     4745 +        if (!(manc & IXGBE_MANC_RCV_TCO_EN))
     4746 +                return FALSE;
     4747 +
     4748 +        if (hw->mac.type <= ixgbe_mac_X540) {
     4749 +                factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
     4750 +                if (factps & IXGBE_FACTPS_MNGCG)
     4751 +                        return FALSE;
     4752 +        }
     4753 +
     4754 +        return TRUE;
     4755 +}
     4756 +
     4757 +/**
     4758 + *  ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
     4759 + *  @hw: pointer to hardware structure
     4760 + *  @speed: new link speed
     4761 + *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
     4762 + *
     4763 + *  Set the link speed in the MAC and/or PHY register and restarts link.
     4764 + **/
     4765 +s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
     4766 +                                          ixgbe_link_speed speed,
     4767 +                                          bool autoneg_wait_to_complete)
     4768 +{
     4769 +        ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
     4770 +        ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
     4771 +        s32 status = IXGBE_SUCCESS;
     4772 +        u32 speedcnt = 0;
     4773 +        u32 i = 0;
     4774 +        bool autoneg, link_up = FALSE;
     4775 +
     4776 +        DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
     4777 +
     4778 +        /* Mask off requested but non-supported speeds */
     4779 +        status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
     4780 +        if (status != IXGBE_SUCCESS)
     4781 +                return status;
     4782 +
     4783 +        speed &= link_speed;
     4784 +
     4785 +        /* Try each speed one by one, highest priority first.  We do this in
     4786 +         * software because 10Gb fiber doesn't support speed autonegotiation.
     4787 +         */
     4788 +        if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
     4789 +                speedcnt++;
     4790 +                highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
     4791 +
     4792 +                /* If we already have link at this speed, just jump out */
     4793 +                status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
     4794 +                if (status != IXGBE_SUCCESS)
     4795 +                        return status;
     4796 +
     4797 +                if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
     4798 +                        goto out;
     4799 +
     4800 +                /* Set the module link speed */
     4801 +                switch (hw->phy.media_type) {
     4802 +                case ixgbe_media_type_fiber_fixed:
     4803 +                case ixgbe_media_type_fiber:
     4804 +                        ixgbe_set_rate_select_speed(hw,
     4805 +                                                    IXGBE_LINK_SPEED_10GB_FULL);
     4806 +                        break;
     4807 +                case ixgbe_media_type_fiber_qsfp:
     4808 +                        /* QSFP module automatically detects MAC link speed */
     4809 +                        break;
     4810 +                default:
     4811 +                        DEBUGOUT("Unexpected media type.\n");
     4812 +                        break;
     4813 +                }
     4814 +
     4815 +                /* Allow module to change analog characteristics (1G->10G) */
     4816 +                msec_delay(40);
     4817 +
     4818 +                status = ixgbe_setup_mac_link(hw,
     4819 +                                              IXGBE_LINK_SPEED_10GB_FULL,
     4820 +                                              autoneg_wait_to_complete);
     4821 +                if (status != IXGBE_SUCCESS)
     4822 +                        return status;
     4823 +
     4824 +                /* Flap the Tx laser if it has not already been done */
     4825 +                ixgbe_flap_tx_laser(hw);
     4826 +
     4827 +                /* Wait for the controller to acquire link.  Per IEEE 802.3ap,
     4828 +                 * Section 73.10.2, we may have to wait up to 500ms if KR is
     4829 +                 * attempted.  82599 uses the same timing for 10g SFI.
     4830 +                 */
     4831 +                for (i = 0; i < 5; i++) {
     4832 +                        /* Wait for the link partner to also set speed */
     4833 +                        msec_delay(100);
     4834 +
     4835 +                        /* If we have link, just jump out */
     4836 +                        status = ixgbe_check_link(hw, &link_speed,
     4837 +                                                  &link_up, FALSE);
     4838 +                        if (status != IXGBE_SUCCESS)
     4839 +                                return status;
     4840 +
     4841 +                        if (link_up)
     4842 +                                goto out;
     4843 +                }
     4844 +        }
     4845 +
     4846 +        if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
     4847 +                speedcnt++;
     4848 +                if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
     4849 +                        highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
     4850 +
     4851 +                /* If we already have link at this speed, just jump out */
     4852 +                status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
     4853 +                if (status != IXGBE_SUCCESS)
     4854 +                        return status;
     4855 +
     4856 +                if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
     4857 +                        goto out;
     4858 +
     4859 +                /* Set the module link speed */
     4860 +                switch (hw->phy.media_type) {
     4861 +                case ixgbe_media_type_fiber_fixed:
     4862 +                case ixgbe_media_type_fiber:
     4863 +                        ixgbe_set_rate_select_speed(hw,
     4864 +                                                    IXGBE_LINK_SPEED_1GB_FULL);
     4865 +                        break;
     4866 +                case ixgbe_media_type_fiber_qsfp:
     4867 +                        /* QSFP module automatically detects link speed */
     4868 +                        break;
     4869 +                default:
     4870 +                        DEBUGOUT("Unexpected media type.\n");
     4871 +                        break;
     4872 +                }
     4873 +
     4874 +                /* Allow module to change analog characteristics (10G->1G) */
     4875 +                msec_delay(40);
     4876 +
     4877 +                status = ixgbe_setup_mac_link(hw,
     4878 +                                              IXGBE_LINK_SPEED_1GB_FULL,
     4879 +                                              autoneg_wait_to_complete);
     4880 +                if (status != IXGBE_SUCCESS)
     4881 +                        return status;
     4882 +
     4883 +                /* Flap the Tx laser if it has not already been done */
     4884 +                ixgbe_flap_tx_laser(hw);
     4885 +
     4886 +                /* Wait for the link partner to also set speed */
     4887 +                msec_delay(100);
     4888 +
     4889 +                /* If we have link, just jump out */
     4890 +                status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
     4891 +                if (status != IXGBE_SUCCESS)
     4892 +                        return status;
     4893 +
     4894 +                if (link_up)
     4895 +                        goto out;
     4896 +        }
     4897 +
     4898 +        /* We didn't get link.  Configure back to the highest speed we tried,
     4899 +         * (if there was more than one).  We call ourselves back with just the
     4900 +         * single highest speed that the user requested.
     4901 +         */
     4902 +        if (speedcnt > 1)
     4903 +                status = ixgbe_setup_mac_link_multispeed_fiber(hw,
     4904 +                                                      highest_link_speed,
     4905 +                                                      autoneg_wait_to_complete);
     4906 +
     4907 +out:
     4908 +        /* Set autoneg_advertised value based on input link speed */
     4909 +        hw->phy.autoneg_advertised = 0;
     4910 +
     4911 +        if (speed & IXGBE_LINK_SPEED_10GB_FULL)
     4912 +                hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
     4913 +
     4914 +        if (speed & IXGBE_LINK_SPEED_1GB_FULL)
     4915 +                hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
     4916 +
     4917 +        return status;
     4918 +}
     4919 +
     4920 +/**
     4921 + *  ixgbe_set_soft_rate_select_speed - Set module link speed
     4922 + *  @hw: pointer to hardware structure
     4923 + *  @speed: link speed to set
     4924 + *
     4925 + *  Set module link speed via the soft rate select.
     4926 + */
     4927 +void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
     4928 +                                        ixgbe_link_speed speed)
     4929 +{
     4930 +        s32 status;
     4931 +        u8 rs, eeprom_data;
     4932 +
     4933 +        switch (speed) {
     4934 +        case IXGBE_LINK_SPEED_10GB_FULL:
     4935 +                /* one bit mask same as setting on */
     4936 +                rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
     4937 +                break;
     4938 +        case IXGBE_LINK_SPEED_1GB_FULL:
     4939 +                rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
     4940 +                break;
     4941 +        default:
     4942 +                DEBUGOUT("Invalid fixed module speed\n");
     4943 +                return;
     4944 +        }
     4945 +
     4946 +        /* Set RS0 */
     4947 +        status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
     4948 +                                           IXGBE_I2C_EEPROM_DEV_ADDR2,
     4949 +                                           &eeprom_data);
     4950 +        if (status) {
     4951 +                DEBUGOUT("Failed to read Rx Rate Select RS0\n");
     4952 +                goto out;
     4953 +        }
     4954 +
     4955 +        eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
     4956 +
     4957 +        status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
     4958 +                                            IXGBE_I2C_EEPROM_DEV_ADDR2,
     4959 +                                            eeprom_data);
     4960 +        if (status) {
     4961 +                DEBUGOUT("Failed to write Rx Rate Select RS0\n");
     4962 +                goto out;
     4963 +        }
     4964 +
     4965 +        /* Set RS1 */
     4966 +        status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
     4967 +                                           IXGBE_I2C_EEPROM_DEV_ADDR2,
     4968 +                                           &eeprom_data);
     4969 +        if (status) {
     4970 +                DEBUGOUT("Failed to read Rx Rate Select RS1\n");
     4971 +                goto out;
     4972 +        }
     4973 +
     4974 +        eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
     4975 +
     4976 +        status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
     4977 +                                            IXGBE_I2C_EEPROM_DEV_ADDR2,
     4978 +                                            eeprom_data);
     4979 +        if (status) {
     4980 +                DEBUGOUT("Failed to write Rx Rate Select RS1\n");
     4981 +                goto out;
     4982 +        }
     4983 +out:
     4984 +        return;
     4985 +}
    
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