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6064 ixgbe needs X550 support
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--- old/usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
+++ new/usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
33 +/*$FreeBSD$*/
34 34
35 35 #include "ixgbe_common.h"
36 36 #include "ixgbe_phy.h"
37 +#include "ixgbe_dcb.h"
38 +#include "ixgbe_dcb_82599.h"
37 39 #include "ixgbe_api.h"
38 40
39 41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 47 u16 count);
46 48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 52
51 53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
53 55 u16 *san_mac_offset);
54 56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 57 u16 words, u16 *data);
56 58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 59 u16 words, u16 *data);
58 60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
59 61 u16 offset);
60 62
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61 63 /**
62 64 * ixgbe_init_ops_generic - Inits function ptrs
63 65 * @hw: pointer to the hardware structure
64 66 *
65 67 * Initialize the function pointers.
66 68 **/
67 69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
68 70 {
69 71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
70 72 struct ixgbe_mac_info *mac = &hw->mac;
71 - u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
73 + u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
72 74
73 75 DEBUGFUNC("ixgbe_init_ops_generic");
74 76
75 77 /* EEPROM */
76 - eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
78 + eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
77 79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
78 80 if (eec & IXGBE_EEC_PRES) {
79 - eeprom->ops.read = &ixgbe_read_eerd_generic;
80 - eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
81 + eeprom->ops.read = ixgbe_read_eerd_generic;
82 + eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
81 83 } else {
82 - eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
84 + eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
83 85 eeprom->ops.read_buffer =
84 - &ixgbe_read_eeprom_buffer_bit_bang_generic;
86 + ixgbe_read_eeprom_buffer_bit_bang_generic;
85 87 }
86 - eeprom->ops.write = &ixgbe_write_eeprom_generic;
87 - eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
88 + eeprom->ops.write = ixgbe_write_eeprom_generic;
89 + eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
88 90 eeprom->ops.validate_checksum =
89 - &ixgbe_validate_eeprom_checksum_generic;
90 - eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
91 - eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
91 + ixgbe_validate_eeprom_checksum_generic;
92 + eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 + eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
92 94
93 95 /* MAC */
94 - mac->ops.init_hw = &ixgbe_init_hw_generic;
96 + mac->ops.init_hw = ixgbe_init_hw_generic;
95 97 mac->ops.reset_hw = NULL;
96 - mac->ops.start_hw = &ixgbe_start_hw_generic;
97 - mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
98 + mac->ops.start_hw = ixgbe_start_hw_generic;
99 + mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
98 100 mac->ops.get_media_type = NULL;
99 101 mac->ops.get_supported_physical_layer = NULL;
100 - mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
101 - mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
102 - mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
103 - mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
104 - mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
105 - mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
106 - mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
102 + mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 + mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 + mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 + mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 + mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 + mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 + mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 + mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 + mac->ops.prot_autoc_write = prot_autoc_write_generic;
107 111
108 112 /* LEDs */
109 - mac->ops.led_on = &ixgbe_led_on_generic;
110 - mac->ops.led_off = &ixgbe_led_off_generic;
111 - mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
112 - mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
113 + mac->ops.led_on = ixgbe_led_on_generic;
114 + mac->ops.led_off = ixgbe_led_off_generic;
115 + mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 + mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
113 117
114 118 /* RAR, Multicast, VLAN */
115 - mac->ops.set_rar = &ixgbe_set_rar_generic;
116 - mac->ops.clear_rar = &ixgbe_clear_rar_generic;
119 + mac->ops.set_rar = ixgbe_set_rar_generic;
120 + mac->ops.clear_rar = ixgbe_clear_rar_generic;
117 121 mac->ops.insert_mac_addr = NULL;
118 122 mac->ops.set_vmdq = NULL;
119 123 mac->ops.clear_vmdq = NULL;
120 - mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
121 - mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
122 - mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
123 - mac->ops.enable_mc = &ixgbe_enable_mc_generic;
124 - mac->ops.disable_mc = &ixgbe_disable_mc_generic;
124 + mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 + mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 + mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 + mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 + mac->ops.disable_mc = ixgbe_disable_mc_generic;
125 129 mac->ops.clear_vfta = NULL;
126 130 mac->ops.set_vfta = NULL;
127 131 mac->ops.set_vlvf = NULL;
128 132 mac->ops.init_uta_tables = NULL;
133 + mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 + mac->ops.disable_rx = ixgbe_disable_rx_generic;
129 135
130 136 /* Flow Control */
131 - mac->ops.fc_enable = &ixgbe_fc_enable_generic;
137 + mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 + mac->ops.setup_fc = ixgbe_setup_fc_generic;
132 139
133 140 /* Link */
134 141 mac->ops.get_link_capabilities = NULL;
135 142 mac->ops.setup_link = NULL;
136 143 mac->ops.check_link = NULL;
144 + mac->ops.dmac_config = NULL;
145 + mac->ops.dmac_update_tcs = NULL;
146 + mac->ops.dmac_config_tcs = NULL;
137 147
138 148 return IXGBE_SUCCESS;
139 149 }
140 150
141 151 /**
142 - * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
143 - * control
144 - * @hw: pointer to hardware structure
152 + * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 + * of flow control
154 + * @hw: pointer to hardware structure
145 155 *
146 - * There are several phys that do not support autoneg flow control. This
147 - * function check the device id to see if the associated phy supports
148 - * autoneg flow control.
156 + * This function returns TRUE if the device supports flow control
157 + * autonegotiation, and FALSE if it does not.
158 + *
149 159 **/
150 -static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
160 +bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
151 161 {
162 + bool supported = FALSE;
163 + ixgbe_link_speed speed;
164 + bool link_up;
152 165
153 166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
154 167
155 - switch (hw->device_id) {
156 - case IXGBE_DEV_ID_X540T:
157 - case IXGBE_DEV_ID_X540T1:
158 - return IXGBE_SUCCESS;
159 - case IXGBE_DEV_ID_82599_T3_LOM:
160 - return IXGBE_SUCCESS;
168 + switch (hw->phy.media_type) {
169 + case ixgbe_media_type_fiber_fixed:
170 + case ixgbe_media_type_fiber_qsfp:
171 + case ixgbe_media_type_fiber:
172 + hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
173 + /* if link is down, assume supported */
174 + if (link_up)
175 + supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
176 + TRUE : FALSE;
177 + else
178 + supported = TRUE;
179 + break;
180 + case ixgbe_media_type_backplane:
181 + supported = TRUE;
182 + break;
183 + case ixgbe_media_type_copper:
184 + /* only some copper devices support flow control autoneg */
185 + switch (hw->device_id) {
186 + case IXGBE_DEV_ID_82599_T3_LOM:
187 + case IXGBE_DEV_ID_X540T:
188 + case IXGBE_DEV_ID_X540T1:
189 + case IXGBE_DEV_ID_X540_BYPASS:
190 + case IXGBE_DEV_ID_X550T:
191 + case IXGBE_DEV_ID_X550T1:
192 + case IXGBE_DEV_ID_X550EM_X_10G_T:
193 + supported = TRUE;
194 + break;
195 + default:
196 + supported = FALSE;
197 + }
161 198 default:
162 - return IXGBE_ERR_FC_NOT_SUPPORTED;
199 + break;
163 200 }
201 +
202 + if (!supported) {
203 + ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
204 + "Device %x does not support flow control autoneg",
205 + hw->device_id);
206 + }
207 +
208 + return supported;
164 209 }
165 210
166 211 /**
167 - * ixgbe_setup_fc - Set up flow control
212 + * ixgbe_setup_fc_generic - Set up flow control
168 213 * @hw: pointer to hardware structure
169 214 *
170 215 * Called at init time to set up flow control.
171 216 **/
172 -static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
217 +s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
173 218 {
174 219 s32 ret_val = IXGBE_SUCCESS;
175 220 u32 reg = 0, reg_bp = 0;
176 221 u16 reg_cu = 0;
222 + bool locked = FALSE;
177 223
178 - DEBUGFUNC("ixgbe_setup_fc");
224 + DEBUGFUNC("ixgbe_setup_fc_generic");
179 225
180 - /*
181 - * Validate the requested mode. Strict IEEE mode does not allow
182 - * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
183 - */
226 + /* Validate the requested mode */
184 227 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
185 - DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
228 + ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
229 + "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
186 230 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
187 231 goto out;
188 232 }
189 233
190 234 /*
191 235 * 10gig parts do not have a word in the EEPROM to determine the
192 236 * default flow control setting, so we explicitly set it to full.
193 237 */
194 238 if (hw->fc.requested_mode == ixgbe_fc_default)
195 239 hw->fc.requested_mode = ixgbe_fc_full;
196 240
197 241 /*
198 242 * Set up the 1G and 10G flow control advertisement registers so the
199 243 * HW will be able to do fc autoneg once the cable is plugged in. If
200 244 * we link at 10G, the 1G advertisement is harmless and vice versa.
201 245 */
202 246 switch (hw->phy.media_type) {
203 - case ixgbe_media_type_fiber:
204 247 case ixgbe_media_type_backplane:
248 + /* some MAC's need RMW protection on AUTOC */
249 + ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
250 + if (ret_val != IXGBE_SUCCESS)
251 + goto out;
252 +
253 + /* only backplane uses autoc so fall though */
254 + case ixgbe_media_type_fiber_fixed:
255 + case ixgbe_media_type_fiber_qsfp:
256 + case ixgbe_media_type_fiber:
205 257 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 - reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
258 +
207 259 break;
208 260 case ixgbe_media_type_copper:
209 261 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 262 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
211 263 break;
212 264 default:
213 265 break;
214 266 }
215 267
216 268 /*
217 269 * The possible values of fc.requested_mode are:
218 270 * 0: Flow control is completely disabled
219 271 * 1: Rx flow control is enabled (we can receive pause frames,
220 272 * but not send pause frames).
221 273 * 2: Tx flow control is enabled (we can send pause frames but
222 274 * we do not support receiving pause frames).
223 275 * 3: Both Rx and Tx flow control (symmetric) are enabled.
224 276 * other: Invalid.
225 277 */
226 278 switch (hw->fc.requested_mode) {
227 279 case ixgbe_fc_none:
228 280 /* Flow control completely disabled by software override. */
229 281 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
230 282 if (hw->phy.media_type == ixgbe_media_type_backplane)
231 283 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
232 284 IXGBE_AUTOC_ASM_PAUSE);
233 285 else if (hw->phy.media_type == ixgbe_media_type_copper)
234 286 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
235 287 break;
236 288 case ixgbe_fc_tx_pause:
237 289 /*
238 290 * Tx Flow control is enabled, and Rx Flow control is
239 291 * disabled by software override.
240 292 */
241 293 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
242 294 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
243 295 if (hw->phy.media_type == ixgbe_media_type_backplane) {
244 296 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
245 297 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
246 298 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
247 299 reg_cu |= IXGBE_TAF_ASM_PAUSE;
248 300 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
249 301 }
250 302 break;
251 303 case ixgbe_fc_rx_pause:
252 304 /*
253 305 * Rx Flow control is enabled and Tx Flow control is
254 306 * disabled by software override. Since there really
255 307 * isn't a way to advertise that we are capable of RX
256 308 * Pause ONLY, we will advertise that we support both
257 309 * symmetric and asymmetric Rx PAUSE, as such we fall
258 310 * through to the fc_full statement. Later, we will
259 311 * disable the adapter's ability to send PAUSE frames.
260 312 */
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261 313 case ixgbe_fc_full:
262 314 /* Flow control (both Rx and Tx) is enabled by SW override. */
263 315 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
264 316 if (hw->phy.media_type == ixgbe_media_type_backplane)
265 317 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
266 318 IXGBE_AUTOC_ASM_PAUSE;
267 319 else if (hw->phy.media_type == ixgbe_media_type_copper)
268 320 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
269 321 break;
270 322 default:
271 - DEBUGOUT("Flow control param set incorrectly\n");
323 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
324 + "Flow control param set incorrectly\n");
272 325 ret_val = IXGBE_ERR_CONFIG;
273 326 goto out;
327 + break;
274 328 }
275 329
276 - if (hw->mac.type != ixgbe_mac_X540) {
330 + if (hw->mac.type < ixgbe_mac_X540) {
277 331 /*
278 332 * Enable auto-negotiation between the MAC & PHY;
279 333 * the MAC will advertise clause 37 flow control.
280 334 */
281 335 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
282 336 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
283 337
284 338 /* Disable AN timeout */
285 339 if (hw->fc.strict_ieee)
286 340 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
287 341
288 342 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
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289 343 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
290 344 }
291 345
292 346 /*
293 347 * AUTOC restart handles negotiation of 1G and 10G on backplane
294 348 * and copper. There is no need to set the PCS1GCTL register.
295 349 *
296 350 */
297 351 if (hw->phy.media_type == ixgbe_media_type_backplane) {
298 352 reg_bp |= IXGBE_AUTOC_AN_RESTART;
299 - IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
353 + ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
354 + if (ret_val)
355 + goto out;
300 356 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
301 - (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
357 + (ixgbe_device_supports_autoneg_fc(hw))) {
302 358 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
303 359 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
304 360 }
305 361
306 - DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
362 + DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
307 363 out:
308 364 return ret_val;
309 365 }
310 366
311 367 /**
312 368 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
313 369 * @hw: pointer to hardware structure
314 370 *
315 371 * Starts the hardware by filling the bus info structure and media type, clears
316 372 * all on chip counters, initializes receive address registers, multicast
317 373 * table, VLAN filter table, calls routine to set up link and flow control
318 374 * settings, and leaves transmit and receive units disabled and uninitialized
319 375 **/
320 376 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
321 377 {
322 378 s32 ret_val;
323 379 u32 ctrl_ext;
324 380
325 381 DEBUGFUNC("ixgbe_start_hw_generic");
326 382
327 383 /* Set the media type */
328 384 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
329 385
330 386 /* PHY ops initialization must be done in reset_hw() */
331 387
332 388 /* Clear the VLAN filter table */
333 389 hw->mac.ops.clear_vfta(hw);
334 390
335 391 /* Clear statistics registers */
336 392 hw->mac.ops.clear_hw_cntrs(hw);
337 393
338 394 /* Set No Snoop Disable */
339 395 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
340 396 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
341 397 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
342 398 IXGBE_WRITE_FLUSH(hw);
343 399
344 400 /* Setup flow control */
345 401 ret_val = ixgbe_setup_fc(hw);
346 402 if (ret_val != IXGBE_SUCCESS)
347 403 goto out;
348 404
349 405 /* Clear adapter stopped flag */
350 406 hw->adapter_stopped = FALSE;
351 407
352 408 out:
353 409 return ret_val;
354 410 }
355 411
356 412 /**
357 413 * ixgbe_start_hw_gen2 - Init sequence for common device family
358 414 * @hw: pointer to hw structure
359 415 *
360 416 * Performs the init sequence common to the second generation
361 417 * of 10 GbE devices.
362 418 * Devices in the second generation:
363 419 * 82599
364 420 * X540
365 421 **/
366 422 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
367 423 {
368 424 u32 i;
369 425 u32 regval;
370 426
371 427 /* Clear the rate limiters */
372 428 for (i = 0; i < hw->mac.max_tx_queues; i++) {
373 429 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
374 430 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
375 431 }
376 432 IXGBE_WRITE_FLUSH(hw);
377 433
378 434 /* Disable relaxed ordering */
379 435 for (i = 0; i < hw->mac.max_tx_queues; i++) {
380 436 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
381 437 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
382 438 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
383 439 }
384 440
385 441 for (i = 0; i < hw->mac.max_rx_queues; i++) {
386 442 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
387 443 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
388 444 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
389 445 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
390 446 }
391 447
392 448 return IXGBE_SUCCESS;
393 449 }
394 450
395 451 /**
396 452 * ixgbe_init_hw_generic - Generic hardware initialization
397 453 * @hw: pointer to hardware structure
398 454 *
399 455 * Initialize the hardware by resetting the hardware, filling the bus info
400 456 * structure and media type, clears all on chip counters, initializes receive
401 457 * address registers, multicast table, VLAN filter table, calls routine to set
402 458 * up link and flow control settings, and leaves transmit and receive units
403 459 * disabled and uninitialized
404 460 **/
405 461 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
406 462 {
407 463 s32 status;
408 464
409 465 DEBUGFUNC("ixgbe_init_hw_generic");
410 466
411 467 /* Reset the hardware */
412 468 status = hw->mac.ops.reset_hw(hw);
413 469
414 470 if (status == IXGBE_SUCCESS) {
415 471 /* Start the HW */
416 472 status = hw->mac.ops.start_hw(hw);
417 473 }
418 474
419 475 return status;
420 476 }
421 477
422 478 /**
423 479 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
424 480 * @hw: pointer to hardware structure
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425 481 *
426 482 * Clears all hardware statistics counters by reading them from the hardware
427 483 * Statistics counters are clear on read.
428 484 **/
429 485 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
430 486 {
431 487 u16 i = 0;
432 488
433 489 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
434 490
435 - (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
436 - (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
437 - (void) IXGBE_READ_REG(hw, IXGBE_ERRBC);
438 - (void) IXGBE_READ_REG(hw, IXGBE_MSPDC);
491 + IXGBE_READ_REG(hw, IXGBE_CRCERRS);
492 + IXGBE_READ_REG(hw, IXGBE_ILLERRC);
493 + IXGBE_READ_REG(hw, IXGBE_ERRBC);
494 + IXGBE_READ_REG(hw, IXGBE_MSPDC);
439 495 for (i = 0; i < 8; i++)
440 - (void) IXGBE_READ_REG(hw, IXGBE_MPC(i));
496 + IXGBE_READ_REG(hw, IXGBE_MPC(i));
441 497
442 - (void) IXGBE_READ_REG(hw, IXGBE_MLFC);
443 - (void) IXGBE_READ_REG(hw, IXGBE_MRFC);
444 - (void) IXGBE_READ_REG(hw, IXGBE_RLEC);
445 - (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC);
446 - (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
498 + IXGBE_READ_REG(hw, IXGBE_MLFC);
499 + IXGBE_READ_REG(hw, IXGBE_MRFC);
500 + IXGBE_READ_REG(hw, IXGBE_RLEC);
501 + IXGBE_READ_REG(hw, IXGBE_LXONTXC);
502 + IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
447 503 if (hw->mac.type >= ixgbe_mac_82599EB) {
448 - (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
449 - (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
504 + IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
505 + IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
450 506 } else {
451 - (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC);
452 - (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
507 + IXGBE_READ_REG(hw, IXGBE_LXONRXC);
508 + IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
453 509 }
454 510
455 511 for (i = 0; i < 8; i++) {
456 - (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
457 - (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
512 + IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
513 + IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
458 514 if (hw->mac.type >= ixgbe_mac_82599EB) {
459 - (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
460 - (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
515 + IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
516 + IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
461 517 } else {
462 - (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
463 - (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
518 + IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
519 + IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
464 520 }
465 521 }
466 522 if (hw->mac.type >= ixgbe_mac_82599EB)
467 523 for (i = 0; i < 8; i++)
468 - (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
469 - (void) IXGBE_READ_REG(hw, IXGBE_PRC64);
470 - (void) IXGBE_READ_REG(hw, IXGBE_PRC127);
471 - (void) IXGBE_READ_REG(hw, IXGBE_PRC255);
472 - (void) IXGBE_READ_REG(hw, IXGBE_PRC511);
473 - (void) IXGBE_READ_REG(hw, IXGBE_PRC1023);
474 - (void) IXGBE_READ_REG(hw, IXGBE_PRC1522);
475 - (void) IXGBE_READ_REG(hw, IXGBE_GPRC);
476 - (void) IXGBE_READ_REG(hw, IXGBE_BPRC);
477 - (void) IXGBE_READ_REG(hw, IXGBE_MPRC);
478 - (void) IXGBE_READ_REG(hw, IXGBE_GPTC);
479 - (void) IXGBE_READ_REG(hw, IXGBE_GORCL);
480 - (void) IXGBE_READ_REG(hw, IXGBE_GORCH);
481 - (void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
482 - (void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
524 + IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
525 + IXGBE_READ_REG(hw, IXGBE_PRC64);
526 + IXGBE_READ_REG(hw, IXGBE_PRC127);
527 + IXGBE_READ_REG(hw, IXGBE_PRC255);
528 + IXGBE_READ_REG(hw, IXGBE_PRC511);
529 + IXGBE_READ_REG(hw, IXGBE_PRC1023);
530 + IXGBE_READ_REG(hw, IXGBE_PRC1522);
531 + IXGBE_READ_REG(hw, IXGBE_GPRC);
532 + IXGBE_READ_REG(hw, IXGBE_BPRC);
533 + IXGBE_READ_REG(hw, IXGBE_MPRC);
534 + IXGBE_READ_REG(hw, IXGBE_GPTC);
535 + IXGBE_READ_REG(hw, IXGBE_GORCL);
536 + IXGBE_READ_REG(hw, IXGBE_GORCH);
537 + IXGBE_READ_REG(hw, IXGBE_GOTCL);
538 + IXGBE_READ_REG(hw, IXGBE_GOTCH);
483 539 if (hw->mac.type == ixgbe_mac_82598EB)
484 540 for (i = 0; i < 8; i++)
485 - (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
486 - (void) IXGBE_READ_REG(hw, IXGBE_RUC);
487 - (void) IXGBE_READ_REG(hw, IXGBE_RFC);
488 - (void) IXGBE_READ_REG(hw, IXGBE_ROC);
489 - (void) IXGBE_READ_REG(hw, IXGBE_RJC);
490 - (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC);
491 - (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC);
492 - (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC);
493 - (void) IXGBE_READ_REG(hw, IXGBE_TORL);
494 - (void) IXGBE_READ_REG(hw, IXGBE_TORH);
495 - (void) IXGBE_READ_REG(hw, IXGBE_TPR);
496 - (void) IXGBE_READ_REG(hw, IXGBE_TPT);
497 - (void) IXGBE_READ_REG(hw, IXGBE_PTC64);
498 - (void) IXGBE_READ_REG(hw, IXGBE_PTC127);
499 - (void) IXGBE_READ_REG(hw, IXGBE_PTC255);
500 - (void) IXGBE_READ_REG(hw, IXGBE_PTC511);
501 - (void) IXGBE_READ_REG(hw, IXGBE_PTC1023);
502 - (void) IXGBE_READ_REG(hw, IXGBE_PTC1522);
503 - (void) IXGBE_READ_REG(hw, IXGBE_MPTC);
504 - (void) IXGBE_READ_REG(hw, IXGBE_BPTC);
541 + IXGBE_READ_REG(hw, IXGBE_RNBC(i));
542 + IXGBE_READ_REG(hw, IXGBE_RUC);
543 + IXGBE_READ_REG(hw, IXGBE_RFC);
544 + IXGBE_READ_REG(hw, IXGBE_ROC);
545 + IXGBE_READ_REG(hw, IXGBE_RJC);
546 + IXGBE_READ_REG(hw, IXGBE_MNGPRC);
547 + IXGBE_READ_REG(hw, IXGBE_MNGPDC);
548 + IXGBE_READ_REG(hw, IXGBE_MNGPTC);
549 + IXGBE_READ_REG(hw, IXGBE_TORL);
550 + IXGBE_READ_REG(hw, IXGBE_TORH);
551 + IXGBE_READ_REG(hw, IXGBE_TPR);
552 + IXGBE_READ_REG(hw, IXGBE_TPT);
553 + IXGBE_READ_REG(hw, IXGBE_PTC64);
554 + IXGBE_READ_REG(hw, IXGBE_PTC127);
555 + IXGBE_READ_REG(hw, IXGBE_PTC255);
556 + IXGBE_READ_REG(hw, IXGBE_PTC511);
557 + IXGBE_READ_REG(hw, IXGBE_PTC1023);
558 + IXGBE_READ_REG(hw, IXGBE_PTC1522);
559 + IXGBE_READ_REG(hw, IXGBE_MPTC);
560 + IXGBE_READ_REG(hw, IXGBE_BPTC);
505 561 for (i = 0; i < 16; i++) {
506 - (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i));
507 - (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i));
562 + IXGBE_READ_REG(hw, IXGBE_QPRC(i));
563 + IXGBE_READ_REG(hw, IXGBE_QPTC(i));
508 564 if (hw->mac.type >= ixgbe_mac_82599EB) {
509 - (void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
510 - (void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
511 - (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
512 - (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
513 - (void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
565 + IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
566 + IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
567 + IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
568 + IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
569 + IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
514 570 } else {
515 - (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i));
516 - (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i));
571 + IXGBE_READ_REG(hw, IXGBE_QBRC(i));
572 + IXGBE_READ_REG(hw, IXGBE_QBTC(i));
517 573 }
518 574 }
519 575
520 - if (hw->mac.type == ixgbe_mac_X540) {
576 + if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
521 577 if (hw->phy.id == 0)
522 - (void) ixgbe_identify_phy(hw);
578 + ixgbe_identify_phy(hw);
523 579 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
524 580 IXGBE_MDIO_PCS_DEV_TYPE, &i);
525 581 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
526 582 IXGBE_MDIO_PCS_DEV_TYPE, &i);
527 583 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
528 584 IXGBE_MDIO_PCS_DEV_TYPE, &i);
529 585 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
530 586 IXGBE_MDIO_PCS_DEV_TYPE, &i);
531 587 }
532 588
533 589 return IXGBE_SUCCESS;
534 590 }
535 591
536 592 /**
537 593 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
538 594 * @hw: pointer to hardware structure
539 595 * @pba_num: stores the part number string from the EEPROM
540 596 * @pba_num_size: part number string buffer length
541 597 *
542 598 * Reads the part number string from the EEPROM.
543 599 **/
544 600 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
545 601 u32 pba_num_size)
546 602 {
547 603 s32 ret_val;
548 604 u16 data;
549 605 u16 pba_ptr;
550 606 u16 offset;
551 607 u16 length;
552 608
553 609 DEBUGFUNC("ixgbe_read_pba_string_generic");
554 610
555 611 if (pba_num == NULL) {
556 612 DEBUGOUT("PBA string buffer was null\n");
557 613 return IXGBE_ERR_INVALID_ARGUMENT;
558 614 }
559 615
560 616 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
561 617 if (ret_val) {
562 618 DEBUGOUT("NVM Read Error\n");
563 619 return ret_val;
564 620 }
565 621
566 622 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
567 623 if (ret_val) {
568 624 DEBUGOUT("NVM Read Error\n");
569 625 return ret_val;
570 626 }
571 627
572 628 /*
573 629 * if data is not ptr guard the PBA must be in legacy format which
574 630 * means pba_ptr is actually our second data word for the PBA number
575 631 * and we can decode it into an ascii string
576 632 */
577 633 if (data != IXGBE_PBANUM_PTR_GUARD) {
578 634 DEBUGOUT("NVM PBA number is not stored as string\n");
579 635
580 636 /* we will need 11 characters to store the PBA */
581 637 if (pba_num_size < 11) {
582 638 DEBUGOUT("PBA string buffer too small\n");
583 639 return IXGBE_ERR_NO_SPACE;
584 640 }
585 641
586 642 /* extract hex string from data and pba_ptr */
587 643 pba_num[0] = (data >> 12) & 0xF;
588 644 pba_num[1] = (data >> 8) & 0xF;
589 645 pba_num[2] = (data >> 4) & 0xF;
590 646 pba_num[3] = data & 0xF;
591 647 pba_num[4] = (pba_ptr >> 12) & 0xF;
592 648 pba_num[5] = (pba_ptr >> 8) & 0xF;
593 649 pba_num[6] = '-';
594 650 pba_num[7] = 0;
595 651 pba_num[8] = (pba_ptr >> 4) & 0xF;
596 652 pba_num[9] = pba_ptr & 0xF;
597 653
598 654 /* put a null character on the end of our string */
599 655 pba_num[10] = '\0';
600 656
601 657 /* switch all the data but the '-' to hex char */
602 658 for (offset = 0; offset < 10; offset++) {
603 659 if (pba_num[offset] < 0xA)
604 660 pba_num[offset] += '0';
605 661 else if (pba_num[offset] < 0x10)
606 662 pba_num[offset] += 'A' - 0xA;
607 663 }
608 664
609 665 return IXGBE_SUCCESS;
610 666 }
611 667
612 668 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
613 669 if (ret_val) {
614 670 DEBUGOUT("NVM Read Error\n");
615 671 return ret_val;
616 672 }
617 673
618 674 if (length == 0xFFFF || length == 0) {
619 675 DEBUGOUT("NVM PBA number section invalid length\n");
620 676 return IXGBE_ERR_PBA_SECTION;
621 677 }
622 678
623 679 /* check if pba_num buffer is big enough */
624 680 if (pba_num_size < (((u32)length * 2) - 1)) {
625 681 DEBUGOUT("PBA string buffer too small\n");
626 682 return IXGBE_ERR_NO_SPACE;
627 683 }
628 684
629 685 /* trim pba length from start of string */
630 686 pba_ptr++;
631 687 length--;
632 688
633 689 for (offset = 0; offset < length; offset++) {
634 690 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
635 691 if (ret_val) {
636 692 DEBUGOUT("NVM Read Error\n");
637 693 return ret_val;
638 694 }
639 695 pba_num[offset * 2] = (u8)(data >> 8);
640 696 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
641 697 }
642 698 pba_num[offset * 2] = '\0';
643 699
644 700 return IXGBE_SUCCESS;
645 701 }
646 702
647 703 /**
648 704 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
649 705 * @hw: pointer to hardware structure
650 706 * @pba_num: stores the part number from the EEPROM
651 707 *
652 708 * Reads the part number from the EEPROM.
653 709 **/
654 710 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
655 711 {
656 712 s32 ret_val;
657 713 u16 data;
658 714
659 715 DEBUGFUNC("ixgbe_read_pba_num_generic");
660 716
661 717 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
662 718 if (ret_val) {
663 719 DEBUGOUT("NVM Read Error\n");
664 720 return ret_val;
665 721 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
666 722 DEBUGOUT("NVM Not supported\n");
667 723 return IXGBE_NOT_IMPLEMENTED;
668 724 }
669 725 *pba_num = (u32)(data << 16);
670 726
671 727 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
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672 728 if (ret_val) {
673 729 DEBUGOUT("NVM Read Error\n");
674 730 return ret_val;
675 731 }
676 732 *pba_num |= data;
677 733
678 734 return IXGBE_SUCCESS;
679 735 }
680 736
681 737 /**
738 + * ixgbe_read_pba_raw
739 + * @hw: pointer to the HW structure
740 + * @eeprom_buf: optional pointer to EEPROM image
741 + * @eeprom_buf_size: size of EEPROM image in words
742 + * @max_pba_block_size: PBA block size limit
743 + * @pba: pointer to output PBA structure
744 + *
745 + * Reads PBA from EEPROM image when eeprom_buf is not NULL.
746 + * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
747 + *
748 + **/
749 +s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
750 + u32 eeprom_buf_size, u16 max_pba_block_size,
751 + struct ixgbe_pba *pba)
752 +{
753 + s32 ret_val;
754 + u16 pba_block_size;
755 +
756 + if (pba == NULL)
757 + return IXGBE_ERR_PARAM;
758 +
759 + if (eeprom_buf == NULL) {
760 + ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
761 + &pba->word[0]);
762 + if (ret_val)
763 + return ret_val;
764 + } else {
765 + if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
766 + pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
767 + pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
768 + } else {
769 + return IXGBE_ERR_PARAM;
770 + }
771 + }
772 +
773 + if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
774 + if (pba->pba_block == NULL)
775 + return IXGBE_ERR_PARAM;
776 +
777 + ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
778 + eeprom_buf_size,
779 + &pba_block_size);
780 + if (ret_val)
781 + return ret_val;
782 +
783 + if (pba_block_size > max_pba_block_size)
784 + return IXGBE_ERR_PARAM;
785 +
786 + if (eeprom_buf == NULL) {
787 + ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
788 + pba_block_size,
789 + pba->pba_block);
790 + if (ret_val)
791 + return ret_val;
792 + } else {
793 + if (eeprom_buf_size > (u32)(pba->word[1] +
794 + pba_block_size)) {
795 + memcpy(pba->pba_block,
796 + &eeprom_buf[pba->word[1]],
797 + pba_block_size * sizeof(u16));
798 + } else {
799 + return IXGBE_ERR_PARAM;
800 + }
801 + }
802 + }
803 +
804 + return IXGBE_SUCCESS;
805 +}
806 +
807 +/**
808 + * ixgbe_write_pba_raw
809 + * @hw: pointer to the HW structure
810 + * @eeprom_buf: optional pointer to EEPROM image
811 + * @eeprom_buf_size: size of EEPROM image in words
812 + * @pba: pointer to PBA structure
813 + *
814 + * Writes PBA to EEPROM image when eeprom_buf is not NULL.
815 + * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
816 + *
817 + **/
818 +s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
819 + u32 eeprom_buf_size, struct ixgbe_pba *pba)
820 +{
821 + s32 ret_val;
822 +
823 + if (pba == NULL)
824 + return IXGBE_ERR_PARAM;
825 +
826 + if (eeprom_buf == NULL) {
827 + ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
828 + &pba->word[0]);
829 + if (ret_val)
830 + return ret_val;
831 + } else {
832 + if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
833 + eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
834 + eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
835 + } else {
836 + return IXGBE_ERR_PARAM;
837 + }
838 + }
839 +
840 + if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
841 + if (pba->pba_block == NULL)
842 + return IXGBE_ERR_PARAM;
843 +
844 + if (eeprom_buf == NULL) {
845 + ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
846 + pba->pba_block[0],
847 + pba->pba_block);
848 + if (ret_val)
849 + return ret_val;
850 + } else {
851 + if (eeprom_buf_size > (u32)(pba->word[1] +
852 + pba->pba_block[0])) {
853 + memcpy(&eeprom_buf[pba->word[1]],
854 + pba->pba_block,
855 + pba->pba_block[0] * sizeof(u16));
856 + } else {
857 + return IXGBE_ERR_PARAM;
858 + }
859 + }
860 + }
861 +
862 + return IXGBE_SUCCESS;
863 +}
864 +
865 +/**
866 + * ixgbe_get_pba_block_size
867 + * @hw: pointer to the HW structure
868 + * @eeprom_buf: optional pointer to EEPROM image
869 + * @eeprom_buf_size: size of EEPROM image in words
870 + * @pba_data_size: pointer to output variable
871 + *
872 + * Returns the size of the PBA block in words. Function operates on EEPROM
873 + * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
874 + * EEPROM device.
875 + *
876 + **/
877 +s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
878 + u32 eeprom_buf_size, u16 *pba_block_size)
879 +{
880 + s32 ret_val;
881 + u16 pba_word[2];
882 + u16 length;
883 +
884 + DEBUGFUNC("ixgbe_get_pba_block_size");
885 +
886 + if (eeprom_buf == NULL) {
887 + ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
888 + &pba_word[0]);
889 + if (ret_val)
890 + return ret_val;
891 + } else {
892 + if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
893 + pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
894 + pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
895 + } else {
896 + return IXGBE_ERR_PARAM;
897 + }
898 + }
899 +
900 + if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
901 + if (eeprom_buf == NULL) {
902 + ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
903 + &length);
904 + if (ret_val)
905 + return ret_val;
906 + } else {
907 + if (eeprom_buf_size > pba_word[1])
908 + length = eeprom_buf[pba_word[1] + 0];
909 + else
910 + return IXGBE_ERR_PARAM;
911 + }
912 +
913 + if (length == 0xFFFF || length == 0)
914 + return IXGBE_ERR_PBA_SECTION;
915 + } else {
916 + /* PBA number in legacy format, there is no PBA Block. */
917 + length = 0;
918 + }
919 +
920 + if (pba_block_size != NULL)
921 + *pba_block_size = length;
922 +
923 + return IXGBE_SUCCESS;
924 +}
925 +
926 +/**
682 927 * ixgbe_get_mac_addr_generic - Generic get MAC address
683 928 * @hw: pointer to hardware structure
684 929 * @mac_addr: Adapter MAC address
685 930 *
686 931 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
687 932 * A reset of the adapter must be performed prior to calling this function
688 933 * in order for the MAC address to have been loaded from the EEPROM into RAR0
689 934 **/
690 935 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
691 936 {
692 937 u32 rar_high;
693 938 u32 rar_low;
694 939 u16 i;
695 940
696 941 DEBUGFUNC("ixgbe_get_mac_addr_generic");
697 942
698 943 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
699 944 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
700 945
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701 946 for (i = 0; i < 4; i++)
702 947 mac_addr[i] = (u8)(rar_low >> (i*8));
703 948
704 949 for (i = 0; i < 2; i++)
705 950 mac_addr[i+4] = (u8)(rar_high >> (i*8));
706 951
707 952 return IXGBE_SUCCESS;
708 953 }
709 954
710 955 /**
711 - * ixgbe_get_bus_info_generic - Generic set PCI bus info
956 + * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
712 957 * @hw: pointer to hardware structure
958 + * @link_status: the link status returned by the PCI config space
713 959 *
714 - * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
960 + * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
715 961 **/
716 -s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
962 +void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
717 963 {
718 964 struct ixgbe_mac_info *mac = &hw->mac;
719 - u16 link_status;
720 965
721 - DEBUGFUNC("ixgbe_get_bus_info_generic");
966 + if (hw->bus.type == ixgbe_bus_type_unknown)
967 + hw->bus.type = ixgbe_bus_type_pci_express;
722 968
723 - hw->bus.type = ixgbe_bus_type_pci_express;
724 -
725 - /* Get the negotiated link width and speed from PCI config space */
726 - link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
727 -
728 969 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
729 970 case IXGBE_PCI_LINK_WIDTH_1:
730 971 hw->bus.width = ixgbe_bus_width_pcie_x1;
731 972 break;
732 973 case IXGBE_PCI_LINK_WIDTH_2:
733 974 hw->bus.width = ixgbe_bus_width_pcie_x2;
734 975 break;
735 976 case IXGBE_PCI_LINK_WIDTH_4:
736 977 hw->bus.width = ixgbe_bus_width_pcie_x4;
737 978 break;
738 979 case IXGBE_PCI_LINK_WIDTH_8:
739 980 hw->bus.width = ixgbe_bus_width_pcie_x8;
740 981 break;
741 982 default:
742 983 hw->bus.width = ixgbe_bus_width_unknown;
743 984 break;
744 985 }
745 986
746 987 switch (link_status & IXGBE_PCI_LINK_SPEED) {
747 988 case IXGBE_PCI_LINK_SPEED_2500:
748 989 hw->bus.speed = ixgbe_bus_speed_2500;
749 990 break;
750 991 case IXGBE_PCI_LINK_SPEED_5000:
751 992 hw->bus.speed = ixgbe_bus_speed_5000;
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752 993 break;
753 994 case IXGBE_PCI_LINK_SPEED_8000:
754 995 hw->bus.speed = ixgbe_bus_speed_8000;
755 996 break;
756 997 default:
757 998 hw->bus.speed = ixgbe_bus_speed_unknown;
758 999 break;
759 1000 }
760 1001
761 1002 mac->ops.set_lan_id(hw);
1003 +}
762 1004
1005 +/**
1006 + * ixgbe_get_bus_info_generic - Generic set PCI bus info
1007 + * @hw: pointer to hardware structure
1008 + *
1009 + * Gets the PCI bus info (speed, width, type) then calls helper function to
1010 + * store this data within the ixgbe_hw structure.
1011 + **/
1012 +s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1013 +{
1014 + u16 link_status;
1015 +
1016 + DEBUGFUNC("ixgbe_get_bus_info_generic");
1017 +
1018 + /* Get the negotiated link width and speed from PCI config space */
1019 + link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1020 +
1021 + ixgbe_set_pci_config_data_generic(hw, link_status);
1022 +
763 1023 return IXGBE_SUCCESS;
764 1024 }
765 1025
766 1026 /**
767 1027 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
768 1028 * @hw: pointer to the HW structure
769 1029 *
770 1030 * Determines the LAN function id by reading memory-mapped registers
771 1031 * and swaps the port value if requested.
772 1032 **/
773 1033 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
774 1034 {
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775 1035 struct ixgbe_bus_info *bus = &hw->bus;
776 1036 u32 reg;
777 1037
778 1038 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
779 1039
780 1040 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
781 1041 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
782 1042 bus->lan_id = bus->func;
783 1043
784 1044 /* check for a port swap */
785 - reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1045 + reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
786 1046 if (reg & IXGBE_FACTPS_LFS)
787 1047 bus->func ^= 0x1;
788 1048 }
789 1049
790 1050 /**
791 1051 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
792 1052 * @hw: pointer to hardware structure
793 1053 *
794 1054 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
795 1055 * disables transmit and receive units. The adapter_stopped flag is used by
796 1056 * the shared code and drivers to determine if the adapter is in a stopped
797 1057 * state and should not touch the hardware.
798 1058 **/
799 1059 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
800 1060 {
801 1061 u32 reg_val;
802 1062 u16 i;
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803 1063
804 1064 DEBUGFUNC("ixgbe_stop_adapter_generic");
805 1065
806 1066 /*
807 1067 * Set the adapter_stopped flag so other driver functions stop touching
808 1068 * the hardware
809 1069 */
810 1070 hw->adapter_stopped = TRUE;
811 1071
812 1072 /* Disable the receive unit */
813 - IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1073 + ixgbe_disable_rx(hw);
814 1074
815 1075 /* Clear interrupt mask to stop interrupts from being generated */
816 1076 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
817 1077
818 1078 /* Clear any pending interrupts, flush previous writes */
819 - (void) IXGBE_READ_REG(hw, IXGBE_EICR);
1079 + IXGBE_READ_REG(hw, IXGBE_EICR);
820 1080
821 1081 /* Disable the transmit unit. Each queue must be disabled. */
822 1082 for (i = 0; i < hw->mac.max_tx_queues; i++)
823 1083 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
824 1084
825 1085 /* Disable the receive unit by stopping each queue */
826 1086 for (i = 0; i < hw->mac.max_rx_queues; i++) {
827 1087 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
828 1088 reg_val &= ~IXGBE_RXDCTL_ENABLE;
829 1089 reg_val |= IXGBE_RXDCTL_SWFLSH;
830 1090 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
831 1091 }
832 1092
833 1093 /* flush all queues disables */
834 1094 IXGBE_WRITE_FLUSH(hw);
835 1095 msec_delay(2);
836 1096
837 1097 /*
838 - * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1098 + * Prevent the PCI-E bus from hanging by disabling PCI-E master
839 1099 * access and verify no pending requests
840 1100 */
841 1101 return ixgbe_disable_pcie_master(hw);
842 1102 }
843 1103
844 1104 /**
845 1105 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
846 1106 * @hw: pointer to hardware structure
847 1107 * @index: led number to turn on
848 1108 **/
849 1109 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
850 1110 {
851 1111 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
852 1112
853 1113 DEBUGFUNC("ixgbe_led_on_generic");
854 1114
855 1115 /* To turn on the LED, set mode to ON. */
856 1116 led_reg &= ~IXGBE_LED_MODE_MASK(index);
857 1117 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
858 1118 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
859 1119 IXGBE_WRITE_FLUSH(hw);
860 1120
861 1121 return IXGBE_SUCCESS;
862 1122 }
863 1123
864 1124 /**
865 1125 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
866 1126 * @hw: pointer to hardware structure
867 1127 * @index: led number to turn off
868 1128 **/
869 1129 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
870 1130 {
871 1131 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
872 1132
873 1133 DEBUGFUNC("ixgbe_led_off_generic");
874 1134
875 1135 /* To turn off the LED, set mode to OFF. */
876 1136 led_reg &= ~IXGBE_LED_MODE_MASK(index);
877 1137 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
878 1138 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
879 1139 IXGBE_WRITE_FLUSH(hw);
880 1140
881 1141 return IXGBE_SUCCESS;
882 1142 }
883 1143
884 1144 /**
885 1145 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
886 1146 * @hw: pointer to hardware structure
887 1147 *
888 1148 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
889 1149 * ixgbe_hw struct in order to set up EEPROM access.
890 1150 **/
891 1151 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
892 1152 {
893 1153 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
894 1154 u32 eec;
895 1155 u16 eeprom_size;
896 1156
897 1157 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
898 1158
899 1159 if (eeprom->type == ixgbe_eeprom_uninitialized) {
900 1160 eeprom->type = ixgbe_eeprom_none;
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901 1161 /* Set default semaphore delay to 10ms which is a well
902 1162 * tested value */
903 1163 eeprom->semaphore_delay = 10;
904 1164 /* Clear EEPROM page size, it will be initialized as needed */
905 1165 eeprom->word_page_size = 0;
906 1166
907 1167 /*
908 1168 * Check for EEPROM present first.
909 1169 * If not present leave as none
910 1170 */
911 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1171 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
912 1172 if (eec & IXGBE_EEC_PRES) {
913 1173 eeprom->type = ixgbe_eeprom_spi;
914 1174
915 1175 /*
916 1176 * SPI EEPROM is assumed here. This code would need to
917 1177 * change if a future EEPROM is not SPI.
918 1178 */
919 1179 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
920 1180 IXGBE_EEC_SIZE_SHIFT);
921 1181 eeprom->word_size = 1 << (eeprom_size +
922 1182 IXGBE_EEPROM_WORD_SIZE_SHIFT);
923 1183 }
924 1184
925 1185 if (eec & IXGBE_EEC_ADDR_SIZE)
926 1186 eeprom->address_bits = 16;
927 1187 else
928 1188 eeprom->address_bits = 8;
929 1189 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
930 1190 "%d\n", eeprom->type, eeprom->word_size,
931 1191 eeprom->address_bits);
932 1192 }
933 1193
934 1194 return IXGBE_SUCCESS;
935 1195 }
936 1196
937 1197 /**
938 1198 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
939 1199 * @hw: pointer to hardware structure
940 1200 * @offset: offset within the EEPROM to write
941 1201 * @words: number of word(s)
942 1202 * @data: 16 bit word(s) to write to EEPROM
943 1203 *
944 1204 * Reads 16 bit word(s) from EEPROM through bit-bang method
945 1205 **/
946 1206 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
947 1207 u16 words, u16 *data)
948 1208 {
949 1209 s32 status = IXGBE_SUCCESS;
950 1210 u16 i, count;
951 1211
952 1212 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
953 1213
954 1214 hw->eeprom.ops.init_params(hw);
955 1215
956 1216 if (words == 0) {
957 1217 status = IXGBE_ERR_INVALID_ARGUMENT;
958 1218 goto out;
959 1219 }
960 1220
961 1221 if (offset + words > hw->eeprom.word_size) {
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962 1222 status = IXGBE_ERR_EEPROM;
963 1223 goto out;
964 1224 }
965 1225
966 1226 /*
967 1227 * The EEPROM page size cannot be queried from the chip. We do lazy
968 1228 * initialization. It is worth to do that when we write large buffer.
969 1229 */
970 1230 if ((hw->eeprom.word_page_size == 0) &&
971 1231 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
972 - status = ixgbe_detect_eeprom_page_size_generic(hw, offset);
973 - if (status != IXGBE_SUCCESS)
974 - goto out;
1232 + ixgbe_detect_eeprom_page_size_generic(hw, offset);
975 1233
976 1234 /*
977 1235 * We cannot hold synchronization semaphores for too long
978 1236 * to avoid other entity starvation. However it is more efficient
979 1237 * to read in bursts than synchronizing access for each word.
980 1238 */
981 1239 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
982 1240 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
983 1241 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
984 1242 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
985 1243 count, &data[i]);
986 1244
987 1245 if (status != IXGBE_SUCCESS)
988 1246 break;
989 1247 }
990 1248
991 1249 out:
992 1250 return status;
993 1251 }
994 1252
995 1253 /**
996 1254 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
997 1255 * @hw: pointer to hardware structure
998 1256 * @offset: offset within the EEPROM to be written to
999 1257 * @words: number of word(s)
1000 1258 * @data: 16 bit word(s) to be written to the EEPROM
1001 1259 *
1002 1260 * If ixgbe_eeprom_update_checksum is not called after this function, the
1003 1261 * EEPROM will most likely contain an invalid checksum.
1004 1262 **/
1005 1263 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1006 1264 u16 words, u16 *data)
1007 1265 {
1008 1266 s32 status;
1009 1267 u16 word;
1010 1268 u16 page_size;
1011 1269 u16 i;
1012 1270 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1013 1271
1014 1272 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1015 1273
1016 1274 /* Prepare the EEPROM for writing */
1017 1275 status = ixgbe_acquire_eeprom(hw);
1018 1276
1019 1277 if (status == IXGBE_SUCCESS) {
1020 1278 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1021 1279 ixgbe_release_eeprom(hw);
1022 1280 status = IXGBE_ERR_EEPROM;
1023 1281 }
1024 1282 }
1025 1283
1026 1284 if (status == IXGBE_SUCCESS) {
1027 1285 for (i = 0; i < words; i++) {
1028 1286 ixgbe_standby_eeprom(hw);
1029 1287
1030 1288 /* Send the WRITE ENABLE command (8 bit opcode ) */
1031 1289 ixgbe_shift_out_eeprom_bits(hw,
1032 1290 IXGBE_EEPROM_WREN_OPCODE_SPI,
1033 1291 IXGBE_EEPROM_OPCODE_BITS);
1034 1292
1035 1293 ixgbe_standby_eeprom(hw);
1036 1294
1037 1295 /*
1038 1296 * Some SPI eeproms use the 8th address bit embedded
1039 1297 * in the opcode
1040 1298 */
1041 1299 if ((hw->eeprom.address_bits == 8) &&
1042 1300 ((offset + i) >= 128))
1043 1301 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1044 1302
1045 1303 /* Send the Write command (8-bit opcode + addr) */
1046 1304 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1047 1305 IXGBE_EEPROM_OPCODE_BITS);
1048 1306 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1049 1307 hw->eeprom.address_bits);
1050 1308
1051 1309 page_size = hw->eeprom.word_page_size;
1052 1310
1053 1311 /* Send the data in burst via SPI*/
1054 1312 do {
1055 1313 word = data[i];
1056 1314 word = (word >> 8) | (word << 8);
1057 1315 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1058 1316
1059 1317 if (page_size == 0)
1060 1318 break;
1061 1319
1062 1320 /* do not wrap around page */
1063 1321 if (((offset + i) & (page_size - 1)) ==
1064 1322 (page_size - 1))
1065 1323 break;
1066 1324 } while (++i < words);
1067 1325
1068 1326 ixgbe_standby_eeprom(hw);
1069 1327 msec_delay(10);
1070 1328 }
1071 1329 /* Done with writing - release the EEPROM */
1072 1330 ixgbe_release_eeprom(hw);
1073 1331 }
1074 1332
1075 1333 return status;
1076 1334 }
1077 1335
1078 1336 /**
1079 1337 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1080 1338 * @hw: pointer to hardware structure
1081 1339 * @offset: offset within the EEPROM to be written to
1082 1340 * @data: 16 bit word to be written to the EEPROM
1083 1341 *
1084 1342 * If ixgbe_eeprom_update_checksum is not called after this function, the
1085 1343 * EEPROM will most likely contain an invalid checksum.
1086 1344 **/
1087 1345 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1088 1346 {
1089 1347 s32 status;
1090 1348
1091 1349 DEBUGFUNC("ixgbe_write_eeprom_generic");
1092 1350
1093 1351 hw->eeprom.ops.init_params(hw);
1094 1352
1095 1353 if (offset >= hw->eeprom.word_size) {
1096 1354 status = IXGBE_ERR_EEPROM;
1097 1355 goto out;
1098 1356 }
1099 1357
1100 1358 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1101 1359
1102 1360 out:
1103 1361 return status;
1104 1362 }
1105 1363
1106 1364 /**
1107 1365 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1108 1366 * @hw: pointer to hardware structure
1109 1367 * @offset: offset within the EEPROM to be read
1110 1368 * @data: read 16 bit words(s) from EEPROM
1111 1369 * @words: number of word(s)
1112 1370 *
1113 1371 * Reads 16 bit word(s) from EEPROM through bit-bang method
1114 1372 **/
1115 1373 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1116 1374 u16 words, u16 *data)
1117 1375 {
1118 1376 s32 status = IXGBE_SUCCESS;
1119 1377 u16 i, count;
1120 1378
1121 1379 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1122 1380
1123 1381 hw->eeprom.ops.init_params(hw);
1124 1382
1125 1383 if (words == 0) {
1126 1384 status = IXGBE_ERR_INVALID_ARGUMENT;
1127 1385 goto out;
1128 1386 }
1129 1387
1130 1388 if (offset + words > hw->eeprom.word_size) {
1131 1389 status = IXGBE_ERR_EEPROM;
1132 1390 goto out;
1133 1391 }
1134 1392
1135 1393 /*
1136 1394 * We cannot hold synchronization semaphores for too long
1137 1395 * to avoid other entity starvation. However it is more efficient
1138 1396 * to read in bursts than synchronizing access for each word.
1139 1397 */
1140 1398 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1141 1399 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1142 1400 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1143 1401
1144 1402 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1145 1403 count, &data[i]);
1146 1404
1147 1405 if (status != IXGBE_SUCCESS)
1148 1406 break;
1149 1407 }
1150 1408
1151 1409 out:
1152 1410 return status;
1153 1411 }
1154 1412
1155 1413 /**
1156 1414 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1157 1415 * @hw: pointer to hardware structure
1158 1416 * @offset: offset within the EEPROM to be read
1159 1417 * @words: number of word(s)
1160 1418 * @data: read 16 bit word(s) from EEPROM
1161 1419 *
1162 1420 * Reads 16 bit word(s) from EEPROM through bit-bang method
1163 1421 **/
1164 1422 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1165 1423 u16 words, u16 *data)
1166 1424 {
1167 1425 s32 status;
1168 1426 u16 word_in;
1169 1427 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1170 1428 u16 i;
1171 1429
1172 1430 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1173 1431
1174 1432 /* Prepare the EEPROM for reading */
1175 1433 status = ixgbe_acquire_eeprom(hw);
1176 1434
1177 1435 if (status == IXGBE_SUCCESS) {
1178 1436 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1179 1437 ixgbe_release_eeprom(hw);
1180 1438 status = IXGBE_ERR_EEPROM;
1181 1439 }
1182 1440 }
1183 1441
1184 1442 if (status == IXGBE_SUCCESS) {
1185 1443 for (i = 0; i < words; i++) {
1186 1444 ixgbe_standby_eeprom(hw);
1187 1445 /*
1188 1446 * Some SPI eeproms use the 8th address bit embedded
1189 1447 * in the opcode
1190 1448 */
1191 1449 if ((hw->eeprom.address_bits == 8) &&
1192 1450 ((offset + i) >= 128))
1193 1451 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1194 1452
1195 1453 /* Send the READ command (opcode + addr) */
1196 1454 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1197 1455 IXGBE_EEPROM_OPCODE_BITS);
1198 1456 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1199 1457 hw->eeprom.address_bits);
1200 1458
1201 1459 /* Read the data. */
1202 1460 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1203 1461 data[i] = (word_in >> 8) | (word_in << 8);
1204 1462 }
1205 1463
1206 1464 /* End this read operation */
1207 1465 ixgbe_release_eeprom(hw);
1208 1466 }
1209 1467
1210 1468 return status;
1211 1469 }
1212 1470
1213 1471 /**
1214 1472 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1215 1473 * @hw: pointer to hardware structure
1216 1474 * @offset: offset within the EEPROM to be read
1217 1475 * @data: read 16 bit value from EEPROM
1218 1476 *
1219 1477 * Reads 16 bit value from EEPROM through bit-bang method
1220 1478 **/
1221 1479 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1222 1480 u16 *data)
1223 1481 {
1224 1482 s32 status;
1225 1483
1226 1484 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1227 1485
1228 1486 hw->eeprom.ops.init_params(hw);
1229 1487
1230 1488 if (offset >= hw->eeprom.word_size) {
1231 1489 status = IXGBE_ERR_EEPROM;
1232 1490 goto out;
1233 1491 }
1234 1492
1235 1493 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1236 1494
1237 1495 out:
1238 1496 return status;
1239 1497 }
1240 1498
1241 1499 /**
1242 1500 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1243 1501 * @hw: pointer to hardware structure
1244 1502 * @offset: offset of word in the EEPROM to read
1245 1503 * @words: number of word(s)
1246 1504 * @data: 16 bit word(s) from the EEPROM
1247 1505 *
1248 1506 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1249 1507 **/
1250 1508 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1251 1509 u16 words, u16 *data)
1252 1510 {
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268 lines elided |
↑ open up ↑ |
1253 1511 u32 eerd;
1254 1512 s32 status = IXGBE_SUCCESS;
1255 1513 u32 i;
1256 1514
1257 1515 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1258 1516
1259 1517 hw->eeprom.ops.init_params(hw);
1260 1518
1261 1519 if (words == 0) {
1262 1520 status = IXGBE_ERR_INVALID_ARGUMENT;
1521 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1263 1522 goto out;
1264 1523 }
1265 1524
1266 1525 if (offset >= hw->eeprom.word_size) {
1267 1526 status = IXGBE_ERR_EEPROM;
1527 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1268 1528 goto out;
1269 1529 }
1270 1530
1271 1531 for (i = 0; i < words; i++) {
1272 - eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1532 + eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1273 1533 IXGBE_EEPROM_RW_REG_START;
1274 1534
1275 1535 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1276 1536 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1277 1537
1278 1538 if (status == IXGBE_SUCCESS) {
1279 1539 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1280 1540 IXGBE_EEPROM_RW_REG_DATA);
1281 1541 } else {
1282 1542 DEBUGOUT("Eeprom read timed out\n");
1283 1543 goto out;
1284 1544 }
1285 1545 }
1286 1546 out:
1287 1547 return status;
1288 1548 }
1289 1549
1290 1550 /**
1291 1551 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1292 1552 * @hw: pointer to hardware structure
1293 1553 * @offset: offset within the EEPROM to be used as a scratch pad
1294 1554 *
1295 1555 * Discover EEPROM page size by writing marching data at given offset.
1296 1556 * This function is called only when we are writing a new large buffer
1297 1557 * at given offset so the data would be overwritten anyway.
1298 1558 **/
1299 1559 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1300 1560 u16 offset)
1301 1561 {
1302 1562 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1303 1563 s32 status = IXGBE_SUCCESS;
1304 1564 u16 i;
1305 1565
1306 1566 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1307 1567
1308 1568 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1309 1569 data[i] = i;
1310 1570
1311 1571 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1312 1572 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1313 1573 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1314 1574 hw->eeprom.word_page_size = 0;
1315 1575 if (status != IXGBE_SUCCESS)
1316 1576 goto out;
1317 1577
1318 1578 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1319 1579 if (status != IXGBE_SUCCESS)
1320 1580 goto out;
1321 1581
1322 1582 /*
1323 1583 * When writing in burst more than the actual page size
1324 1584 * EEPROM address wraps around current page.
1325 1585 */
1326 1586 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1327 1587
1328 1588 DEBUGOUT1("Detected EEPROM page size = %d words.",
1329 1589 hw->eeprom.word_page_size);
1330 1590 out:
1331 1591 return status;
1332 1592 }
1333 1593
1334 1594 /**
1335 1595 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1336 1596 * @hw: pointer to hardware structure
1337 1597 * @offset: offset of word in the EEPROM to read
1338 1598 * @data: word read from the EEPROM
1339 1599 *
1340 1600 * Reads a 16 bit word from the EEPROM using the EERD register.
1341 1601 **/
1342 1602 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1343 1603 {
1344 1604 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1345 1605 }
1346 1606
1347 1607 /**
1348 1608 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1349 1609 * @hw: pointer to hardware structure
1350 1610 * @offset: offset of word in the EEPROM to write
1351 1611 * @words: number of word(s)
1352 1612 * @data: word(s) write to the EEPROM
1353 1613 *
1354 1614 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1355 1615 **/
1356 1616 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1357 1617 u16 words, u16 *data)
1358 1618 {
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1359 1619 u32 eewr;
1360 1620 s32 status = IXGBE_SUCCESS;
1361 1621 u16 i;
1362 1622
1363 1623 DEBUGFUNC("ixgbe_write_eewr_generic");
1364 1624
1365 1625 hw->eeprom.ops.init_params(hw);
1366 1626
1367 1627 if (words == 0) {
1368 1628 status = IXGBE_ERR_INVALID_ARGUMENT;
1629 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1369 1630 goto out;
1370 1631 }
1371 1632
1372 1633 if (offset >= hw->eeprom.word_size) {
1373 1634 status = IXGBE_ERR_EEPROM;
1635 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1374 1636 goto out;
1375 1637 }
1376 1638
1377 1639 for (i = 0; i < words; i++) {
1378 1640 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1379 1641 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1380 1642 IXGBE_EEPROM_RW_REG_START;
1381 1643
1382 1644 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1383 1645 if (status != IXGBE_SUCCESS) {
1384 1646 DEBUGOUT("Eeprom write EEWR timed out\n");
1385 1647 goto out;
1386 1648 }
1387 1649
1388 1650 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1389 1651
1390 1652 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1391 1653 if (status != IXGBE_SUCCESS) {
1392 1654 DEBUGOUT("Eeprom write EEWR timed out\n");
1393 1655 goto out;
1394 1656 }
1395 1657 }
1396 1658
1397 1659 out:
1398 1660 return status;
1399 1661 }
1400 1662
1401 1663 /**
1402 1664 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1403 1665 * @hw: pointer to hardware structure
1404 1666 * @offset: offset of word in the EEPROM to write
1405 1667 * @data: word write to the EEPROM
1406 1668 *
1407 1669 * Write a 16 bit word to the EEPROM using the EEWR register.
1408 1670 **/
1409 1671 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1410 1672 {
1411 1673 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1412 1674 }
1413 1675
1414 1676 /**
1415 1677 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1416 1678 * @hw: pointer to hardware structure
1417 1679 * @ee_reg: EEPROM flag for polling
1418 1680 *
1419 1681 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1420 1682 * read or write is done respectively.
1421 1683 **/
1422 1684 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1423 1685 {
1424 1686 u32 i;
1425 1687 u32 reg;
1426 1688 s32 status = IXGBE_ERR_EEPROM;
1427 1689
1428 1690 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1429 1691
1430 1692 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1431 1693 if (ee_reg == IXGBE_NVM_POLL_READ)
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48 lines elided |
↑ open up ↑ |
1432 1694 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1433 1695 else
1434 1696 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1435 1697
1436 1698 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1437 1699 status = IXGBE_SUCCESS;
1438 1700 break;
1439 1701 }
1440 1702 usec_delay(5);
1441 1703 }
1704 +
1705 + if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1706 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
1707 + "EEPROM read/write done polling timed out");
1708 +
1442 1709 return status;
1443 1710 }
1444 1711
1445 1712 /**
1446 1713 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1447 1714 * @hw: pointer to hardware structure
1448 1715 *
1449 1716 * Prepares EEPROM for access using bit-bang method. This function should
1450 1717 * be called before issuing a command to the EEPROM.
1451 1718 **/
1452 1719 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1453 1720 {
1454 1721 s32 status = IXGBE_SUCCESS;
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3 lines elided |
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1455 1722 u32 eec;
1456 1723 u32 i;
1457 1724
1458 1725 DEBUGFUNC("ixgbe_acquire_eeprom");
1459 1726
1460 1727 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1461 1728 != IXGBE_SUCCESS)
1462 1729 status = IXGBE_ERR_SWFW_SYNC;
1463 1730
1464 1731 if (status == IXGBE_SUCCESS) {
1465 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1732 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1466 1733
1467 1734 /* Request EEPROM Access */
1468 1735 eec |= IXGBE_EEC_REQ;
1469 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1736 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1470 1737
1471 1738 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1472 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1739 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1473 1740 if (eec & IXGBE_EEC_GNT)
1474 1741 break;
1475 1742 usec_delay(5);
1476 1743 }
1477 1744
1478 1745 /* Release if grant not acquired */
1479 1746 if (!(eec & IXGBE_EEC_GNT)) {
1480 1747 eec &= ~IXGBE_EEC_REQ;
1481 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1748 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1482 1749 DEBUGOUT("Could not acquire EEPROM grant\n");
1483 1750
1484 1751 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1485 1752 status = IXGBE_ERR_EEPROM;
1486 1753 }
1487 1754
1488 1755 /* Setup EEPROM for Read/Write */
1489 1756 if (status == IXGBE_SUCCESS) {
1490 1757 /* Clear CS and SK */
1491 1758 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1492 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1759 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1493 1760 IXGBE_WRITE_FLUSH(hw);
1494 1761 usec_delay(1);
1495 1762 }
1496 1763 }
1497 1764 return status;
1498 1765 }
1499 1766
1500 1767 /**
1501 1768 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1502 1769 * @hw: pointer to hardware structure
1503 1770 *
1504 1771 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1505 1772 **/
1506 1773 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1507 1774 {
1508 1775 s32 status = IXGBE_ERR_EEPROM;
1509 1776 u32 timeout = 2000;
1510 1777 u32 i;
1511 1778 u32 swsm;
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9 lines elided |
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1512 1779
1513 1780 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1514 1781
1515 1782
1516 1783 /* Get SMBI software semaphore between device drivers first */
1517 1784 for (i = 0; i < timeout; i++) {
1518 1785 /*
1519 1786 * If the SMBI bit is 0 when we read it, then the bit will be
1520 1787 * set and we have the semaphore
1521 1788 */
1522 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1789 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1523 1790 if (!(swsm & IXGBE_SWSM_SMBI)) {
1524 1791 status = IXGBE_SUCCESS;
1525 1792 break;
1526 1793 }
1527 1794 usec_delay(50);
1528 1795 }
1529 1796
1530 1797 if (i == timeout) {
1531 1798 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1532 1799 "not granted.\n");
1533 1800 /*
1534 1801 * this release is particularly important because our attempts
1535 1802 * above to get the semaphore may have succeeded, and if there
1536 1803 * was a timeout, we should unconditionally clear the semaphore
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4 lines elided |
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1537 1804 * bits to free the driver to make progress
1538 1805 */
1539 1806 ixgbe_release_eeprom_semaphore(hw);
1540 1807
1541 1808 usec_delay(50);
1542 1809 /*
1543 1810 * one last try
1544 1811 * If the SMBI bit is 0 when we read it, then the bit will be
1545 1812 * set and we have the semaphore
1546 1813 */
1547 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1814 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1548 1815 if (!(swsm & IXGBE_SWSM_SMBI))
1549 1816 status = IXGBE_SUCCESS;
1550 1817 }
1551 1818
1552 1819 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1553 1820 if (status == IXGBE_SUCCESS) {
1554 1821 for (i = 0; i < timeout; i++) {
1555 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1822 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1556 1823
1557 1824 /* Set the SW EEPROM semaphore bit to request access */
1558 1825 swsm |= IXGBE_SWSM_SWESMBI;
1559 - IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1826 + IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1560 1827
1561 1828 /*
1562 1829 * If we set the bit successfully then we got the
1563 1830 * semaphore.
1564 1831 */
1565 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1832 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1566 1833 if (swsm & IXGBE_SWSM_SWESMBI)
1567 1834 break;
1568 1835
1569 1836 usec_delay(50);
1570 1837 }
1571 1838
1572 1839 /*
1573 1840 * Release semaphores and return error if SW EEPROM semaphore
1574 1841 * was not granted because we don't have access to the EEPROM
1575 1842 */
1576 1843 if (i >= timeout) {
1577 - DEBUGOUT("SWESMBI Software EEPROM semaphore "
1578 - "not granted.\n");
1844 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
1845 + "SWESMBI Software EEPROM semaphore not granted.\n");
1579 1846 ixgbe_release_eeprom_semaphore(hw);
1580 1847 status = IXGBE_ERR_EEPROM;
1581 1848 }
1582 1849 } else {
1583 - DEBUGOUT("Software semaphore SMBI between device drivers "
1584 - "not granted.\n");
1850 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
1851 + "Software semaphore SMBI between device drivers "
1852 + "not granted.\n");
1585 1853 }
1586 1854
1587 1855 return status;
1588 1856 }
1589 1857
1590 1858 /**
1591 1859 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1592 1860 * @hw: pointer to hardware structure
1593 1861 *
1594 1862 * This function clears hardware semaphore bits.
1595 1863 **/
1596 1864 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1597 1865 {
1598 1866 u32 swsm;
1599 1867
1600 1868 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1601 1869
1602 1870 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1603 1871
1604 1872 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1605 1873 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1606 1874 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1607 1875 IXGBE_WRITE_FLUSH(hw);
1608 1876 }
1609 1877
1610 1878 /**
1611 1879 * ixgbe_ready_eeprom - Polls for EEPROM ready
1612 1880 * @hw: pointer to hardware structure
1613 1881 **/
1614 1882 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1615 1883 {
1616 1884 s32 status = IXGBE_SUCCESS;
1617 1885 u16 i;
1618 1886 u8 spi_stat_reg;
1619 1887
1620 1888 DEBUGFUNC("ixgbe_ready_eeprom");
1621 1889
1622 1890 /*
1623 1891 * Read "Status Register" repeatedly until the LSB is cleared. The
1624 1892 * EEPROM will signal that the command has been completed by clearing
1625 1893 * bit 0 of the internal status register. If it's not cleared within
1626 1894 * 5 milliseconds, then error out.
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1627 1895 */
1628 1896 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1629 1897 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1630 1898 IXGBE_EEPROM_OPCODE_BITS);
1631 1899 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1632 1900 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1633 1901 break;
1634 1902
1635 1903 usec_delay(5);
1636 1904 ixgbe_standby_eeprom(hw);
1637 - };
1905 + }
1638 1906
1639 1907 /*
1640 1908 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1641 1909 * devices (and only 0-5mSec on 5V devices)
1642 1910 */
1643 1911 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1644 1912 DEBUGOUT("SPI EEPROM Status error\n");
1645 1913 status = IXGBE_ERR_EEPROM;
1646 1914 }
1647 1915
1648 1916 return status;
1649 1917 }
1650 1918
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1651 1919 /**
1652 1920 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1653 1921 * @hw: pointer to hardware structure
1654 1922 **/
1655 1923 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1656 1924 {
1657 1925 u32 eec;
1658 1926
1659 1927 DEBUGFUNC("ixgbe_standby_eeprom");
1660 1928
1661 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1929 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1662 1930
1663 1931 /* Toggle CS to flush commands */
1664 1932 eec |= IXGBE_EEC_CS;
1665 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1933 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1666 1934 IXGBE_WRITE_FLUSH(hw);
1667 1935 usec_delay(1);
1668 1936 eec &= ~IXGBE_EEC_CS;
1669 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1937 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1670 1938 IXGBE_WRITE_FLUSH(hw);
1671 1939 usec_delay(1);
1672 1940 }
1673 1941
1674 1942 /**
1675 1943 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1676 1944 * @hw: pointer to hardware structure
1677 1945 * @data: data to send to the EEPROM
1678 1946 * @count: number of bits to shift out
1679 1947 **/
1680 1948 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1681 1949 u16 count)
1682 1950 {
1683 1951 u32 eec;
1684 1952 u32 mask;
1685 1953 u32 i;
1686 1954
1687 1955 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1688 1956
1689 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1957 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1690 1958
1691 1959 /*
1692 1960 * Mask is used to shift "count" bits of "data" out to the EEPROM
1693 1961 * one bit at a time. Determine the starting bit based on count
1694 1962 */
1695 1963 mask = 0x01 << (count - 1);
1696 1964
1697 1965 for (i = 0; i < count; i++) {
1698 1966 /*
1699 1967 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1700 1968 * "1", and then raising and then lowering the clock (the SK
1701 1969 * bit controls the clock input to the EEPROM). A "0" is
1702 1970 * shifted out to the EEPROM by setting "DI" to "0" and then
1703 1971 * raising and then lowering the clock.
1704 1972 */
1705 1973 if (data & mask)
1706 1974 eec |= IXGBE_EEC_DI;
1707 1975 else
1708 1976 eec &= ~IXGBE_EEC_DI;
1709 1977
1710 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1978 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1711 1979 IXGBE_WRITE_FLUSH(hw);
1712 1980
1713 1981 usec_delay(1);
1714 1982
1715 1983 ixgbe_raise_eeprom_clk(hw, &eec);
1716 1984 ixgbe_lower_eeprom_clk(hw, &eec);
1717 1985
1718 1986 /*
1719 1987 * Shift mask to signify next bit of data to shift in to the
1720 1988 * EEPROM
1721 1989 */
1722 1990 mask = mask >> 1;
1723 - };
1991 + }
1724 1992
1725 1993 /* We leave the "DI" bit set to "0" when we leave this routine. */
1726 1994 eec &= ~IXGBE_EEC_DI;
1727 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1995 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1728 1996 IXGBE_WRITE_FLUSH(hw);
1729 1997 }
1730 1998
1731 1999 /**
1732 2000 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1733 2001 * @hw: pointer to hardware structure
1734 2002 **/
1735 2003 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1736 2004 {
1737 2005 u32 eec;
1738 2006 u32 i;
1739 2007 u16 data = 0;
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1740 2008
1741 2009 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1742 2010
1743 2011 /*
1744 2012 * In order to read a register from the EEPROM, we need to shift
1745 2013 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1746 2014 * the clock input to the EEPROM (setting the SK bit), and then reading
1747 2015 * the value of the "DO" bit. During this "shifting in" process the
1748 2016 * "DI" bit should always be clear.
1749 2017 */
1750 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2018 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1751 2019
1752 2020 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1753 2021
1754 2022 for (i = 0; i < count; i++) {
1755 2023 data = data << 1;
1756 2024 ixgbe_raise_eeprom_clk(hw, &eec);
1757 2025
1758 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2026 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1759 2027
1760 2028 eec &= ~(IXGBE_EEC_DI);
1761 2029 if (eec & IXGBE_EEC_DO)
1762 2030 data |= 1;
1763 2031
1764 2032 ixgbe_lower_eeprom_clk(hw, &eec);
1765 2033 }
1766 2034
1767 2035 return data;
1768 2036 }
1769 2037
1770 2038 /**
1771 2039 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1772 2040 * @hw: pointer to hardware structure
1773 2041 * @eec: EEC register's current value
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1774 2042 **/
1775 2043 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1776 2044 {
1777 2045 DEBUGFUNC("ixgbe_raise_eeprom_clk");
1778 2046
1779 2047 /*
1780 2048 * Raise the clock input to the EEPROM
1781 2049 * (setting the SK bit), then delay
1782 2050 */
1783 2051 *eec = *eec | IXGBE_EEC_SK;
1784 - IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2052 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
1785 2053 IXGBE_WRITE_FLUSH(hw);
1786 2054 usec_delay(1);
1787 2055 }
1788 2056
1789 2057 /**
1790 2058 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1791 2059 * @hw: pointer to hardware structure
1792 2060 * @eecd: EECD's current value
1793 2061 **/
1794 2062 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1795 2063 {
1796 2064 DEBUGFUNC("ixgbe_lower_eeprom_clk");
1797 2065
1798 2066 /*
1799 2067 * Lower the clock input to the EEPROM (clearing the SK bit), then
1800 2068 * delay
1801 2069 */
1802 2070 *eec = *eec & ~IXGBE_EEC_SK;
1803 - IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2071 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
1804 2072 IXGBE_WRITE_FLUSH(hw);
1805 2073 usec_delay(1);
1806 2074 }
1807 2075
1808 2076 /**
1809 2077 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1810 2078 * @hw: pointer to hardware structure
1811 2079 **/
1812 2080 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1813 2081 {
1814 2082 u32 eec;
1815 2083
1816 2084 DEBUGFUNC("ixgbe_release_eeprom");
1817 2085
1818 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2086 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1819 2087
1820 2088 eec |= IXGBE_EEC_CS; /* Pull CS high */
1821 2089 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1822 2090
1823 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2091 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1824 2092 IXGBE_WRITE_FLUSH(hw);
1825 2093
1826 2094 usec_delay(1);
1827 2095
1828 2096 /* Stop requesting EEPROM access */
1829 2097 eec &= ~IXGBE_EEC_REQ;
1830 - IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2098 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1831 2099
1832 2100 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1833 2101
1834 2102 /* Delay before attempt to obtain semaphore again to allow FW access */
1835 2103 msec_delay(hw->eeprom.semaphore_delay);
1836 2104 }
1837 2105
1838 2106 /**
1839 2107 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1840 2108 * @hw: pointer to hardware structure
2109 + *
2110 + * Returns a negative error code on error, or the 16-bit checksum
1841 2111 **/
1842 -u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2112 +s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1843 2113 {
1844 2114 u16 i;
1845 2115 u16 j;
1846 2116 u16 checksum = 0;
1847 2117 u16 length = 0;
1848 2118 u16 pointer = 0;
1849 2119 u16 word = 0;
1850 2120
1851 2121 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1852 2122
1853 2123 /* Include 0x0-0x3F in the checksum */
1854 2124 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1855 - if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2125 + if (hw->eeprom.ops.read(hw, i, &word)) {
1856 2126 DEBUGOUT("EEPROM read failed\n");
1857 - break;
2127 + return IXGBE_ERR_EEPROM;
1858 2128 }
1859 2129 checksum += word;
1860 2130 }
1861 2131
1862 2132 /* Include all data from pointers except for the fw pointer */
1863 2133 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1864 - hw->eeprom.ops.read(hw, i, &pointer);
2134 + if (hw->eeprom.ops.read(hw, i, &pointer)) {
2135 + DEBUGOUT("EEPROM read failed\n");
2136 + return IXGBE_ERR_EEPROM;
2137 + }
1865 2138
1866 - /* Make sure the pointer seems valid */
1867 - if (pointer != 0xFFFF && pointer != 0) {
1868 - hw->eeprom.ops.read(hw, pointer, &length);
2139 + /* If the pointer seems invalid */
2140 + if (pointer == 0xFFFF || pointer == 0)
2141 + continue;
1869 2142
1870 - if (length != 0xFFFF && length != 0) {
1871 - for (j = pointer+1; j <= pointer+length; j++) {
1872 - hw->eeprom.ops.read(hw, j, &word);
1873 - checksum += word;
1874 - }
2143 + if (hw->eeprom.ops.read(hw, pointer, &length)) {
2144 + DEBUGOUT("EEPROM read failed\n");
2145 + return IXGBE_ERR_EEPROM;
2146 + }
2147 +
2148 + if (length == 0xFFFF || length == 0)
2149 + continue;
2150 +
2151 + for (j = pointer + 1; j <= pointer + length; j++) {
2152 + if (hw->eeprom.ops.read(hw, j, &word)) {
2153 + DEBUGOUT("EEPROM read failed\n");
2154 + return IXGBE_ERR_EEPROM;
1875 2155 }
2156 + checksum += word;
1876 2157 }
1877 2158 }
1878 2159
1879 2160 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1880 2161
1881 - return checksum;
2162 + return (s32)checksum;
1882 2163 }
1883 2164
1884 2165 /**
1885 2166 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1886 2167 * @hw: pointer to hardware structure
1887 2168 * @checksum_val: calculated checksum
1888 2169 *
1889 2170 * Performs checksum calculation and validates the EEPROM checksum. If the
1890 2171 * caller does not need checksum_val, the value can be NULL.
1891 2172 **/
1892 2173 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1893 2174 u16 *checksum_val)
1894 2175 {
1895 2176 s32 status;
1896 2177 u16 checksum;
1897 2178 u16 read_checksum = 0;
1898 2179
1899 2180 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1900 2181
1901 - /*
1902 - * Read the first word from the EEPROM. If this times out or fails, do
2182 + /* Read the first word from the EEPROM. If this times out or fails, do
1903 2183 * not continue or we could be in for a very long wait while every
1904 2184 * EEPROM read fails
1905 2185 */
1906 2186 status = hw->eeprom.ops.read(hw, 0, &checksum);
2187 + if (status) {
2188 + DEBUGOUT("EEPROM read failed\n");
2189 + return status;
2190 + }
1907 2191
1908 - if (status == IXGBE_SUCCESS) {
1909 - checksum = hw->eeprom.ops.calc_checksum(hw);
2192 + status = hw->eeprom.ops.calc_checksum(hw);
2193 + if (status < 0)
2194 + return status;
1910 2195
1911 - hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2196 + checksum = (u16)(status & 0xffff);
1912 2197
1913 - /*
1914 - * Verify read checksum from EEPROM is the same as
1915 - * calculated checksum
1916 - */
1917 - if (read_checksum != checksum)
1918 - status = IXGBE_ERR_EEPROM_CHECKSUM;
1919 -
1920 - /* If the user cares, return the calculated checksum */
1921 - if (checksum_val)
1922 - *checksum_val = checksum;
1923 - } else {
2198 + status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2199 + if (status) {
1924 2200 DEBUGOUT("EEPROM read failed\n");
2201 + return status;
1925 2202 }
1926 2203
2204 + /* Verify read checksum from EEPROM is the same as
2205 + * calculated checksum
2206 + */
2207 + if (read_checksum != checksum)
2208 + status = IXGBE_ERR_EEPROM_CHECKSUM;
2209 +
2210 + /* If the user cares, return the calculated checksum */
2211 + if (checksum_val)
2212 + *checksum_val = checksum;
2213 +
1927 2214 return status;
1928 2215 }
1929 2216
1930 2217 /**
1931 2218 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1932 2219 * @hw: pointer to hardware structure
1933 2220 **/
1934 2221 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1935 2222 {
1936 2223 s32 status;
1937 2224 u16 checksum;
1938 2225
1939 2226 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1940 2227
1941 - /*
1942 - * Read the first word from the EEPROM. If this times out or fails, do
2228 + /* Read the first word from the EEPROM. If this times out or fails, do
1943 2229 * not continue or we could be in for a very long wait while every
1944 2230 * EEPROM read fails
1945 2231 */
1946 2232 status = hw->eeprom.ops.read(hw, 0, &checksum);
1947 -
1948 - if (status == IXGBE_SUCCESS) {
1949 - checksum = hw->eeprom.ops.calc_checksum(hw);
1950 - status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1951 - checksum);
1952 - } else {
2233 + if (status) {
1953 2234 DEBUGOUT("EEPROM read failed\n");
2235 + return status;
1954 2236 }
1955 2237
2238 + status = hw->eeprom.ops.calc_checksum(hw);
2239 + if (status < 0)
2240 + return status;
2241 +
2242 + checksum = (u16)(status & 0xffff);
2243 +
2244 + status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2245 +
1956 2246 return status;
1957 2247 }
1958 2248
1959 2249 /**
1960 2250 * ixgbe_validate_mac_addr - Validate MAC address
1961 2251 * @mac_addr: pointer to MAC address.
1962 2252 *
1963 2253 * Tests a MAC address to ensure it is a valid Individual Address
1964 2254 **/
1965 2255 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1966 2256 {
1967 2257 s32 status = IXGBE_SUCCESS;
1968 2258
1969 2259 DEBUGFUNC("ixgbe_validate_mac_addr");
1970 2260
1971 2261 /* Make sure it is not a multicast address */
1972 2262 if (IXGBE_IS_MULTICAST(mac_addr)) {
1973 2263 DEBUGOUT("MAC address is multicast\n");
1974 2264 status = IXGBE_ERR_INVALID_MAC_ADDR;
1975 2265 /* Not a broadcast address */
1976 2266 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1977 2267 DEBUGOUT("MAC address is broadcast\n");
1978 2268 status = IXGBE_ERR_INVALID_MAC_ADDR;
1979 2269 /* Reject the zero address */
1980 2270 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1981 2271 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1982 2272 DEBUGOUT("MAC address is all zeros\n");
1983 2273 status = IXGBE_ERR_INVALID_MAC_ADDR;
1984 2274 }
1985 2275 return status;
1986 2276 }
1987 2277
1988 2278 /**
1989 2279 * ixgbe_set_rar_generic - Set Rx address register
1990 2280 * @hw: pointer to hardware structure
1991 2281 * @index: Receive address register to write
1992 2282 * @addr: Address to put into receive address register
1993 2283 * @vmdq: VMDq "set" or "pool" index
1994 2284 * @enable_addr: set flag that address is active
1995 2285 *
1996 2286 * Puts an ethernet address into a receive address register.
1997 2287 **/
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1998 2288 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1999 2289 u32 enable_addr)
2000 2290 {
2001 2291 u32 rar_low, rar_high;
2002 2292 u32 rar_entries = hw->mac.num_rar_entries;
2003 2293
2004 2294 DEBUGFUNC("ixgbe_set_rar_generic");
2005 2295
2006 2296 /* Make sure we are using a valid rar index range */
2007 2297 if (index >= rar_entries) {
2008 - DEBUGOUT1("RAR index %d is out of range.\n", index);
2298 + ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2299 + "RAR index %d is out of range.\n", index);
2009 2300 return IXGBE_ERR_INVALID_ARGUMENT;
2010 2301 }
2011 2302
2012 2303 /* setup VMDq pool selection before this RAR gets enabled */
2013 2304 hw->mac.ops.set_vmdq(hw, index, vmdq);
2014 2305
2015 2306 /*
2016 2307 * HW expects these in little endian so we reverse the byte
2017 2308 * order from network order (big endian) to little endian
2018 2309 */
2019 2310 rar_low = ((u32)addr[0] |
2020 2311 ((u32)addr[1] << 8) |
2021 2312 ((u32)addr[2] << 16) |
2022 2313 ((u32)addr[3] << 24));
2023 2314 /*
2024 2315 * Some parts put the VMDq setting in the extra RAH bits,
2025 2316 * so save everything except the lower 16 bits that hold part
2026 2317 * of the address and the address valid bit.
2027 2318 */
2028 2319 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2029 2320 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2030 2321 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2031 2322
2032 2323 if (enable_addr != 0)
2033 2324 rar_high |= IXGBE_RAH_AV;
2034 2325
2035 2326 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2036 2327 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2037 2328
2038 2329 return IXGBE_SUCCESS;
2039 2330 }
2040 2331
2041 2332 /**
2042 2333 * ixgbe_clear_rar_generic - Remove Rx address register
2043 2334 * @hw: pointer to hardware structure
2044 2335 * @index: Receive address register to write
2045 2336 *
2046 2337 * Clears an ethernet address from a receive address register.
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2047 2338 **/
2048 2339 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2049 2340 {
2050 2341 u32 rar_high;
2051 2342 u32 rar_entries = hw->mac.num_rar_entries;
2052 2343
2053 2344 DEBUGFUNC("ixgbe_clear_rar_generic");
2054 2345
2055 2346 /* Make sure we are using a valid rar index range */
2056 2347 if (index >= rar_entries) {
2057 - DEBUGOUT1("RAR index %d is out of range.\n", index);
2348 + ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2349 + "RAR index %d is out of range.\n", index);
2058 2350 return IXGBE_ERR_INVALID_ARGUMENT;
2059 2351 }
2060 2352
2061 2353 /*
2062 2354 * Some parts put the VMDq setting in the extra RAH bits,
2063 2355 * so save everything except the lower 16 bits that hold part
2064 2356 * of the address and the address valid bit.
2065 2357 */
2066 2358 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2067 2359 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2068 2360
2069 2361 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2070 2362 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2071 2363
2072 2364 /* clear VMDq pool/queue selection for this RAR */
2073 2365 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2074 2366
2075 2367 return IXGBE_SUCCESS;
2076 2368 }
2077 2369
2078 2370 /**
2079 2371 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2080 2372 * @hw: pointer to hardware structure
2081 2373 *
2082 2374 * Places the MAC address in receive address register 0 and clears the rest
2083 2375 * of the receive address registers. Clears the multicast table. Assumes
2084 2376 * the receiver is in reset when the routine is called.
2085 2377 **/
2086 2378 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2087 2379 {
2088 2380 u32 i;
2089 2381 u32 rar_entries = hw->mac.num_rar_entries;
2090 2382
2091 2383 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2092 2384
2093 2385 /*
2094 2386 * If the current mac address is valid, assume it is a software override
2095 2387 * to the permanent address.
2096 2388 * Otherwise, use the permanent address from the eeprom.
2097 2389 */
2098 2390 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2099 2391 IXGBE_ERR_INVALID_MAC_ADDR) {
2100 2392 /* Get the MAC address from the RAR0 for later reference */
2101 2393 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2102 2394
2103 2395 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2104 2396 hw->mac.addr[0], hw->mac.addr[1],
2105 2397 hw->mac.addr[2]);
2106 2398 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2107 2399 hw->mac.addr[4], hw->mac.addr[5]);
2108 2400 } else {
2109 2401 /* Setup the receive address. */
2110 2402 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2111 2403 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2112 2404 hw->mac.addr[0], hw->mac.addr[1],
2113 2405 hw->mac.addr[2]);
2114 2406 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2115 2407 hw->mac.addr[4], hw->mac.addr[5]);
2116 2408
2117 2409 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2118 2410
2119 2411 /* clear VMDq pool/queue selection for RAR 0 */
2120 2412 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2121 2413 }
2122 2414 hw->addr_ctrl.overflow_promisc = 0;
2123 2415
2124 2416 hw->addr_ctrl.rar_used_count = 1;
2125 2417
2126 2418 /* Zero out the other receive addresses. */
2127 2419 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2128 2420 for (i = 1; i < rar_entries; i++) {
2129 2421 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2130 2422 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
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2131 2423 }
2132 2424
2133 2425 /* Clear the MTA */
2134 2426 hw->addr_ctrl.mta_in_use = 0;
2135 2427 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2136 2428
2137 2429 DEBUGOUT(" Clearing MTA\n");
2138 2430 for (i = 0; i < hw->mac.mcft_size; i++)
2139 2431 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2140 2432
2141 - /* Should always be IXGBE_SUCCESS. */
2142 - return ixgbe_init_uta_tables(hw);
2433 + ixgbe_init_uta_tables(hw);
2434 +
2435 + return IXGBE_SUCCESS;
2143 2436 }
2144 2437
2145 2438 /**
2146 2439 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2147 2440 * @hw: pointer to hardware structure
2148 2441 * @addr: new address
2149 2442 *
2150 2443 * Adds it to unused receive address register or goes into promiscuous mode.
2151 2444 **/
2152 2445 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2153 2446 {
2154 2447 u32 rar_entries = hw->mac.num_rar_entries;
2155 2448 u32 rar;
2156 2449
2157 2450 DEBUGFUNC("ixgbe_add_uc_addr");
2158 2451
2159 2452 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2160 2453 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2161 2454
2162 2455 /*
2163 2456 * Place this address in the RAR if there is room,
2164 2457 * else put the controller into promiscuous mode
2165 2458 */
2166 2459 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2167 2460 rar = hw->addr_ctrl.rar_used_count;
2168 2461 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2169 2462 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2170 2463 hw->addr_ctrl.rar_used_count++;
2171 2464 } else {
2172 2465 hw->addr_ctrl.overflow_promisc++;
2173 2466 }
2174 2467
2175 2468 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2176 2469 }
2177 2470
2178 2471 /**
2179 2472 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2180 2473 * @hw: pointer to hardware structure
2181 2474 * @addr_list: the list of new addresses
2182 2475 * @addr_count: number of addresses
2183 2476 * @next: iterator function to walk the address list
2184 2477 *
2185 2478 * The given list replaces any existing list. Clears the secondary addrs from
2186 2479 * receive address registers. Uses unused receive address registers for the
2187 2480 * first secondary addresses, and falls back to promiscuous mode as needed.
2188 2481 *
2189 2482 * Drivers using secondary unicast addresses must set user_set_promisc when
2190 2483 * manually putting the device into promiscuous mode.
2191 2484 **/
2192 2485 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2193 2486 u32 addr_count, ixgbe_mc_addr_itr next)
2194 2487 {
2195 2488 u8 *addr;
2196 2489 u32 i;
2197 2490 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2198 2491 u32 uc_addr_in_use;
2199 2492 u32 fctrl;
2200 2493 u32 vmdq;
2201 2494
2202 2495 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2203 2496
2204 2497 /*
2205 2498 * Clear accounting of old secondary address list,
2206 2499 * don't count RAR[0]
2207 2500 */
2208 2501 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2209 2502 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2210 2503 hw->addr_ctrl.overflow_promisc = 0;
2211 2504
2212 2505 /* Zero out the other receive addresses */
2213 2506 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2214 2507 for (i = 0; i < uc_addr_in_use; i++) {
2215 2508 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2216 2509 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2217 2510 }
2218 2511
2219 2512 /* Add the new addresses */
2220 2513 for (i = 0; i < addr_count; i++) {
2221 2514 DEBUGOUT(" Adding the secondary addresses:\n");
2222 2515 addr = next(hw, &addr_list, &vmdq);
2223 2516 ixgbe_add_uc_addr(hw, addr, vmdq);
2224 2517 }
2225 2518
2226 2519 if (hw->addr_ctrl.overflow_promisc) {
2227 2520 /* enable promisc if not already in overflow or set by user */
2228 2521 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2229 2522 DEBUGOUT(" Entering address overflow promisc mode\n");
2230 2523 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2231 2524 fctrl |= IXGBE_FCTRL_UPE;
2232 2525 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2233 2526 }
2234 2527 } else {
2235 2528 /* only disable if set by overflow, not by user */
2236 2529 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2237 2530 DEBUGOUT(" Leaving address overflow promisc mode\n");
2238 2531 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2239 2532 fctrl &= ~IXGBE_FCTRL_UPE;
2240 2533 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2241 2534 }
2242 2535 }
2243 2536
2244 2537 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2245 2538 return IXGBE_SUCCESS;
2246 2539 }
2247 2540
2248 2541 /**
2249 2542 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2250 2543 * @hw: pointer to hardware structure
2251 2544 * @mc_addr: the multicast address
2252 2545 *
2253 2546 * Extracts the 12 bits, from a multicast address, to determine which
2254 2547 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2255 2548 * incoming rx multicast addresses, to determine the bit-vector to check in
2256 2549 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2257 2550 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2258 2551 * to mc_filter_type.
2259 2552 **/
2260 2553 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2261 2554 {
2262 2555 u32 vector = 0;
2263 2556
2264 2557 DEBUGFUNC("ixgbe_mta_vector");
2265 2558
2266 2559 switch (hw->mac.mc_filter_type) {
2267 2560 case 0: /* use bits [47:36] of the address */
2268 2561 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2269 2562 break;
2270 2563 case 1: /* use bits [46:35] of the address */
2271 2564 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2272 2565 break;
2273 2566 case 2: /* use bits [45:34] of the address */
2274 2567 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2275 2568 break;
2276 2569 case 3: /* use bits [43:32] of the address */
2277 2570 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2278 2571 break;
2279 2572 default: /* Invalid mc_filter_type */
2280 2573 DEBUGOUT("MC filter type param set incorrectly\n");
2281 2574 ASSERT(0);
2282 2575 break;
2283 2576 }
2284 2577
2285 2578 /* vector can only be 12-bits or boundary will be exceeded */
2286 2579 vector &= 0xFFF;
2287 2580 return vector;
2288 2581 }
2289 2582
2290 2583 /**
2291 2584 * ixgbe_set_mta - Set bit-vector in multicast table
2292 2585 * @hw: pointer to hardware structure
2293 2586 * @hash_value: Multicast address hash value
2294 2587 *
2295 2588 * Sets the bit-vector in the multicast table.
2296 2589 **/
2297 2590 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2298 2591 {
2299 2592 u32 vector;
2300 2593 u32 vector_bit;
2301 2594 u32 vector_reg;
2302 2595
2303 2596 DEBUGFUNC("ixgbe_set_mta");
2304 2597
2305 2598 hw->addr_ctrl.mta_in_use++;
2306 2599
2307 2600 vector = ixgbe_mta_vector(hw, mc_addr);
2308 2601 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2309 2602
2310 2603 /*
2311 2604 * The MTA is a register array of 128 32-bit registers. It is treated
2312 2605 * like an array of 4096 bits. We want to set bit
2313 2606 * BitArray[vector_value]. So we figure out what register the bit is
2314 2607 * in, read it, OR in the new bit, then write back the new value. The
2315 2608 * register is determined by the upper 7 bits of the vector value and
2316 2609 * the bit within that register are determined by the lower 5 bits of
2317 2610 * the value.
2318 2611 */
2319 2612 vector_reg = (vector >> 5) & 0x7F;
2320 2613 vector_bit = vector & 0x1F;
2321 2614 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2322 2615 }
2323 2616
2324 2617 /**
2325 2618 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2326 2619 * @hw: pointer to hardware structure
2327 2620 * @mc_addr_list: the list of new multicast addresses
2328 2621 * @mc_addr_count: number of addresses
2329 2622 * @next: iterator function to walk the multicast address list
2330 2623 * @clear: flag, when set clears the table beforehand
2331 2624 *
2332 2625 * When the clear flag is set, the given list replaces any existing list.
2333 2626 * Hashes the given addresses into the multicast table.
2334 2627 **/
2335 2628 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2336 2629 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2337 2630 bool clear)
2338 2631 {
2339 2632 u32 i;
2340 2633 u32 vmdq;
2341 2634
2342 2635 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2343 2636
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2344 2637 /*
2345 2638 * Set the new number of MC addresses that we are being requested to
2346 2639 * use.
2347 2640 */
2348 2641 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2349 2642 hw->addr_ctrl.mta_in_use = 0;
2350 2643
2351 2644 /* Clear mta_shadow */
2352 2645 if (clear) {
2353 2646 DEBUGOUT(" Clearing MTA\n");
2354 - (void) memset(&hw->mac.mta_shadow, 0,
2355 - sizeof(hw->mac.mta_shadow));
2647 + memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2356 2648 }
2357 2649
2358 2650 /* Update mta_shadow */
2359 2651 for (i = 0; i < mc_addr_count; i++) {
2360 2652 DEBUGOUT(" Adding the multicast addresses:\n");
2361 2653 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2362 2654 }
2363 2655
2364 2656 /* Enable mta */
2365 2657 for (i = 0; i < hw->mac.mcft_size; i++)
2366 2658 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2367 2659 hw->mac.mta_shadow[i]);
2368 2660
2369 2661 if (hw->addr_ctrl.mta_in_use > 0)
2370 2662 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2371 2663 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2372 2664
2373 2665 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2374 2666 return IXGBE_SUCCESS;
2375 2667 }
2376 2668
2377 2669 /**
2378 2670 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2379 2671 * @hw: pointer to hardware structure
2380 2672 *
2381 2673 * Enables multicast address in RAR and the use of the multicast hash table.
2382 2674 **/
2383 2675 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2384 2676 {
2385 2677 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2386 2678
2387 2679 DEBUGFUNC("ixgbe_enable_mc_generic");
2388 2680
2389 2681 if (a->mta_in_use > 0)
2390 2682 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2391 2683 hw->mac.mc_filter_type);
2392 2684
2393 2685 return IXGBE_SUCCESS;
2394 2686 }
2395 2687
2396 2688 /**
2397 2689 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2398 2690 * @hw: pointer to hardware structure
2399 2691 *
2400 2692 * Disables multicast address in RAR and the use of the multicast hash table.
2401 2693 **/
2402 2694 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2403 2695 {
2404 2696 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2405 2697
2406 2698 DEBUGFUNC("ixgbe_disable_mc_generic");
2407 2699
2408 2700 if (a->mta_in_use > 0)
2409 2701 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2410 2702
2411 2703 return IXGBE_SUCCESS;
2412 2704 }
2413 2705
2414 2706 /**
2415 2707 * ixgbe_fc_enable_generic - Enable flow control
2416 2708 * @hw: pointer to hardware structure
2417 2709 *
2418 2710 * Enable flow control according to the current settings.
2419 2711 **/
2420 2712 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2421 2713 {
2422 2714 s32 ret_val = IXGBE_SUCCESS;
2423 2715 u32 mflcn_reg, fccfg_reg;
2424 2716 u32 reg;
2425 2717 u32 fcrtl, fcrth;
2426 2718 int i;
2427 2719
2428 2720 DEBUGFUNC("ixgbe_fc_enable_generic");
2429 2721
2430 2722 /* Validate the water mark configuration */
2431 2723 if (!hw->fc.pause_time) {
2432 2724 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2433 2725 goto out;
2434 2726 }
2435 2727
2436 2728 /* Low water mark of zero causes XOFF floods */
2437 2729 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2438 2730 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2439 2731 hw->fc.high_water[i]) {
2440 2732 if (!hw->fc.low_water[i] ||
2441 2733 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2442 2734 DEBUGOUT("Invalid water mark configuration\n");
2443 2735 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2444 2736 goto out;
2445 2737 }
2446 2738 }
2447 2739 }
2448 2740
2449 2741 /* Negotiate the fc mode to use */
2450 2742 ixgbe_fc_autoneg(hw);
2451 2743
2452 2744 /* Disable any previous flow control settings */
2453 2745 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2454 2746 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2455 2747
2456 2748 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2457 2749 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2458 2750
2459 2751 /*
2460 2752 * The possible values of fc.current_mode are:
2461 2753 * 0: Flow control is completely disabled
2462 2754 * 1: Rx flow control is enabled (we can receive pause frames,
2463 2755 * but not send pause frames).
2464 2756 * 2: Tx flow control is enabled (we can send pause frames but
2465 2757 * we do not support receiving pause frames).
2466 2758 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2467 2759 * other: Invalid.
2468 2760 */
2469 2761 switch (hw->fc.current_mode) {
2470 2762 case ixgbe_fc_none:
2471 2763 /*
2472 2764 * Flow control is disabled by software override or autoneg.
2473 2765 * The code below will actually disable it in the HW.
2474 2766 */
2475 2767 break;
2476 2768 case ixgbe_fc_rx_pause:
2477 2769 /*
2478 2770 * Rx Flow control is enabled and Tx Flow control is
2479 2771 * disabled by software override. Since there really
2480 2772 * isn't a way to advertise that we are capable of RX
2481 2773 * Pause ONLY, we will advertise that we support both
2482 2774 * symmetric and asymmetric Rx PAUSE. Later, we will
2483 2775 * disable the adapter's ability to send PAUSE frames.
2484 2776 */
2485 2777 mflcn_reg |= IXGBE_MFLCN_RFCE;
2486 2778 break;
2487 2779 case ixgbe_fc_tx_pause:
2488 2780 /*
2489 2781 * Tx Flow control is enabled, and Rx Flow control is
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2490 2782 * disabled by software override.
2491 2783 */
2492 2784 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2493 2785 break;
2494 2786 case ixgbe_fc_full:
2495 2787 /* Flow control (both Rx and Tx) is enabled by SW override. */
2496 2788 mflcn_reg |= IXGBE_MFLCN_RFCE;
2497 2789 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2498 2790 break;
2499 2791 default:
2500 - DEBUGOUT("Flow control param set incorrectly\n");
2792 + ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2793 + "Flow control param set incorrectly\n");
2501 2794 ret_val = IXGBE_ERR_CONFIG;
2502 2795 goto out;
2796 + break;
2503 2797 }
2504 2798
2505 2799 /* Set 802.3x based flow control settings. */
2506 2800 mflcn_reg |= IXGBE_MFLCN_DPF;
2507 2801 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2508 2802 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2509 2803
2510 2804
2511 2805 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2512 2806 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2513 2807 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2514 2808 hw->fc.high_water[i]) {
2515 2809 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2516 2810 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2517 2811 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2518 2812 } else {
2519 2813 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2520 2814 /*
2521 2815 * In order to prevent Tx hangs when the internal Tx
2522 2816 * switch is enabled we must set the high water mark
2523 - * to the maximum FCRTH value. This allows the Tx
2524 - * switch to function even under heavy Rx workloads.
2817 + * to the Rx packet buffer size - 24KB. This allows
2818 + * the Tx switch to function even under heavy Rx
2819 + * workloads.
2525 2820 */
2526 - fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2821 + fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2527 2822 }
2528 2823
2529 2824 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2530 2825 }
2531 2826
2532 2827 /* Configure pause time (2 TCs per register) */
2533 2828 reg = hw->fc.pause_time * 0x00010001;
2534 2829 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2535 2830 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2536 2831
2537 2832 /* Configure flow control refresh threshold value */
2538 2833 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2539 2834
2540 2835 out:
2541 2836 return ret_val;
2542 2837 }
2543 2838
2544 2839 /**
2545 2840 * ixgbe_negotiate_fc - Negotiate flow control
2546 2841 * @hw: pointer to hardware structure
2547 2842 * @adv_reg: flow control advertised settings
2548 2843 * @lp_reg: link partner's flow control settings
2549 2844 * @adv_sym: symmetric pause bit in advertisement
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2550 2845 * @adv_asm: asymmetric pause bit in advertisement
2551 2846 * @lp_sym: symmetric pause bit in link partner advertisement
2552 2847 * @lp_asm: asymmetric pause bit in link partner advertisement
2553 2848 *
2554 2849 * Find the intersection between advertised settings and link partner's
2555 2850 * advertised settings
2556 2851 **/
2557 2852 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2558 2853 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2559 2854 {
2560 - if ((!(adv_reg)) || (!(lp_reg)))
2855 + if ((!(adv_reg)) || (!(lp_reg))) {
2856 + ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2857 + "Local or link partner's advertised flow control "
2858 + "settings are NULL. Local: %x, link partner: %x\n",
2859 + adv_reg, lp_reg);
2561 2860 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2861 + }
2562 2862
2563 2863 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2564 2864 /*
2565 2865 * Now we need to check if the user selected Rx ONLY
2566 2866 * of pause frames. In this case, we had to advertise
2567 2867 * FULL flow control because we could not advertise RX
2568 2868 * ONLY. Hence, we must now check to see if we need to
2569 2869 * turn OFF the TRANSMISSION of PAUSE frames.
2570 2870 */
2571 2871 if (hw->fc.requested_mode == ixgbe_fc_full) {
2572 2872 hw->fc.current_mode = ixgbe_fc_full;
2573 2873 DEBUGOUT("Flow Control = FULL.\n");
2574 2874 } else {
2575 2875 hw->fc.current_mode = ixgbe_fc_rx_pause;
2576 2876 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2577 2877 }
2578 2878 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2579 2879 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2580 2880 hw->fc.current_mode = ixgbe_fc_tx_pause;
2581 2881 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2582 2882 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2583 2883 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2584 2884 hw->fc.current_mode = ixgbe_fc_rx_pause;
2585 2885 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2586 2886 } else {
2587 2887 hw->fc.current_mode = ixgbe_fc_none;
2588 2888 DEBUGOUT("Flow Control = NONE.\n");
2589 2889 }
2590 2890 return IXGBE_SUCCESS;
2591 2891 }
2592 2892
2593 2893 /**
2594 2894 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2595 2895 * @hw: pointer to hardware structure
2596 2896 *
2597 2897 * Enable flow control according on 1 gig fiber.
2598 2898 **/
2599 2899 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2600 2900 {
2601 2901 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
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30 lines elided |
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2602 2902 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2603 2903
2604 2904 /*
2605 2905 * On multispeed fiber at 1g, bail out if
2606 2906 * - link is up but AN did not complete, or if
2607 2907 * - link is up and AN completed but timed out
2608 2908 */
2609 2909
2610 2910 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2611 2911 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2612 - (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2912 + (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2913 + DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2613 2914 goto out;
2915 + }
2614 2916
2615 2917 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2616 2918 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2617 2919
2618 2920 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2619 2921 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2620 2922 IXGBE_PCS1GANA_ASM_PAUSE,
2621 2923 IXGBE_PCS1GANA_SYM_PAUSE,
2622 2924 IXGBE_PCS1GANA_ASM_PAUSE);
2623 2925
2624 2926 out:
2625 2927 return ret_val;
2626 2928 }
2627 2929
2628 2930 /**
2629 2931 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2630 2932 * @hw: pointer to hardware structure
2631 2933 *
2632 2934 * Enable flow control according to IEEE clause 37.
2633 2935 **/
2634 2936 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
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11 lines elided |
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2635 2937 {
2636 2938 u32 links2, anlp1_reg, autoc_reg, links;
2637 2939 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2638 2940
2639 2941 /*
2640 2942 * On backplane, bail out if
2641 2943 * - backplane autoneg was not completed, or if
2642 2944 * - we are 82599 and link partner is not AN enabled
2643 2945 */
2644 2946 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2645 - if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2947 + if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2948 + DEBUGOUT("Auto-Negotiation did not complete\n");
2646 2949 goto out;
2950 + }
2647 2951
2648 2952 if (hw->mac.type == ixgbe_mac_82599EB) {
2649 2953 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2650 - if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2954 + if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2955 + DEBUGOUT("Link partner is not AN enabled\n");
2651 2956 goto out;
2957 + }
2652 2958 }
2653 2959 /*
2654 2960 * Read the 10g AN autoc and LP ability registers and resolve
2655 2961 * local flow control settings accordingly
2656 2962 */
2657 2963 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2658 2964 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2659 2965
2660 2966 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2661 2967 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2662 2968 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2663 2969
2664 2970 out:
2665 2971 return ret_val;
2666 2972 }
2667 2973
2668 2974 /**
2669 2975 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2670 2976 * @hw: pointer to hardware structure
2671 2977 *
2672 2978 * Enable flow control according to IEEE clause 37.
2673 2979 **/
2674 2980 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2675 2981 {
2676 2982 u16 technology_ability_reg = 0;
2677 2983 u16 lp_technology_ability_reg = 0;
2678 2984
2679 2985 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2680 2986 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2681 2987 &technology_ability_reg);
2682 2988 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2683 2989 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2684 2990 &lp_technology_ability_reg);
2685 2991
2686 2992 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2687 2993 (u32)lp_technology_ability_reg,
2688 2994 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2689 2995 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2690 2996 }
2691 2997
2692 2998 /**
2693 2999 * ixgbe_fc_autoneg - Configure flow control
2694 3000 * @hw: pointer to hardware structure
2695 3001 *
2696 3002 * Compares our advertised flow control capabilities to those advertised by
2697 3003 * our link partner, and determines the proper flow control mode to use.
2698 3004 **/
2699 3005 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2700 3006 {
2701 3007 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2702 3008 ixgbe_link_speed speed;
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41 lines elided |
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2703 3009 bool link_up;
2704 3010
2705 3011 DEBUGFUNC("ixgbe_fc_autoneg");
2706 3012
2707 3013 /*
2708 3014 * AN should have completed when the cable was plugged in.
2709 3015 * Look for reasons to bail out. Bail out if:
2710 3016 * - FC autoneg is disabled, or if
2711 3017 * - link is not up.
2712 3018 */
2713 - if (hw->fc.disable_fc_autoneg)
3019 + if (hw->fc.disable_fc_autoneg) {
3020 + ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3021 + "Flow control autoneg is disabled");
2714 3022 goto out;
3023 + }
2715 3024
2716 3025 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2717 - if (!link_up)
3026 + if (!link_up) {
3027 + ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
2718 3028 goto out;
3029 + }
2719 3030
2720 3031 switch (hw->phy.media_type) {
2721 3032 /* Autoneg flow control on fiber adapters */
3033 + case ixgbe_media_type_fiber_fixed:
3034 + case ixgbe_media_type_fiber_qsfp:
2722 3035 case ixgbe_media_type_fiber:
2723 3036 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2724 3037 ret_val = ixgbe_fc_autoneg_fiber(hw);
2725 3038 break;
2726 3039
2727 3040 /* Autoneg flow control on backplane adapters */
2728 3041 case ixgbe_media_type_backplane:
2729 3042 ret_val = ixgbe_fc_autoneg_backplane(hw);
2730 3043 break;
2731 3044
2732 3045 /* Autoneg flow control on copper adapters */
2733 3046 case ixgbe_media_type_copper:
2734 - if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
3047 + if (ixgbe_device_supports_autoneg_fc(hw))
2735 3048 ret_val = ixgbe_fc_autoneg_copper(hw);
2736 3049 break;
2737 3050
2738 3051 default:
2739 3052 break;
2740 3053 }
2741 3054
2742 3055 out:
2743 3056 if (ret_val == IXGBE_SUCCESS) {
2744 3057 hw->fc.fc_was_autonegged = TRUE;
2745 3058 } else {
2746 3059 hw->fc.fc_was_autonegged = FALSE;
2747 3060 hw->fc.current_mode = hw->fc.requested_mode;
2748 3061 }
2749 3062 }
2750 3063
3064 +/*
3065 + * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3066 + * @hw: pointer to hardware structure
3067 + *
3068 + * System-wide timeout range is encoded in PCIe Device Control2 register.
3069 + *
3070 + * Add 10% to specified maximum and return the number of times to poll for
3071 + * completion timeout, in units of 100 microsec. Never return less than
3072 + * 800 = 80 millisec.
3073 + */
3074 +static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3075 +{
3076 + s16 devctl2;
3077 + u32 pollcnt;
3078 +
3079 + devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3080 + devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3081 +
3082 + switch (devctl2) {
3083 + case IXGBE_PCIDEVCTRL2_65_130ms:
3084 + pollcnt = 1300; /* 130 millisec */
3085 + break;
3086 + case IXGBE_PCIDEVCTRL2_260_520ms:
3087 + pollcnt = 5200; /* 520 millisec */
3088 + break;
3089 + case IXGBE_PCIDEVCTRL2_1_2s:
3090 + pollcnt = 20000; /* 2 sec */
3091 + break;
3092 + case IXGBE_PCIDEVCTRL2_4_8s:
3093 + pollcnt = 80000; /* 8 sec */
3094 + break;
3095 + case IXGBE_PCIDEVCTRL2_17_34s:
3096 + pollcnt = 34000; /* 34 sec */
3097 + break;
3098 + case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3099 + case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3100 + case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3101 + case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3102 + default:
3103 + pollcnt = 800; /* 80 millisec minimum */
3104 + break;
3105 + }
3106 +
3107 + /* add 10% to spec maximum */
3108 + return (pollcnt * 11) / 10;
3109 +}
3110 +
2751 3111 /**
2752 3112 * ixgbe_disable_pcie_master - Disable PCI-express master access
2753 3113 * @hw: pointer to hardware structure
2754 3114 *
2755 3115 * Disables PCI-Express master access and verifies there are no pending
2756 3116 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2757 3117 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2758 3118 * is returned signifying master requests disabled.
2759 3119 **/
2760 3120 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2761 3121 {
2762 3122 s32 status = IXGBE_SUCCESS;
2763 - u32 i;
3123 + u32 i, poll;
3124 + u16 value;
2764 3125
2765 3126 DEBUGFUNC("ixgbe_disable_pcie_master");
2766 3127
2767 3128 /* Always set this bit to ensure any future transactions are blocked */
2768 3129 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2769 3130
2770 - /* Exit if master requets are blocked */
2771 - if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3131 + /* Exit if master requests are blocked */
3132 + if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3133 + IXGBE_REMOVED(hw->hw_addr))
2772 3134 goto out;
2773 3135
2774 3136 /* Poll for master request bit to clear */
2775 3137 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2776 3138 usec_delay(100);
2777 3139 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2778 3140 goto out;
2779 3141 }
2780 3142
2781 3143 /*
2782 3144 * Two consecutive resets are required via CTRL.RST per datasheet
2783 3145 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2784 3146 * of this need. The first reset prevents new master requests from
2785 3147 * being issued by our device. We then must wait 1usec or more for any
2786 3148 * remaining completions from the PCIe bus to trickle in, and then reset
2787 3149 * again to clear out any effects they may have had on our device.
2788 3150 */
2789 3151 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2790 3152 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2791 3153
3154 + if (hw->mac.type >= ixgbe_mac_X550)
3155 + goto out;
3156 +
2792 3157 /*
2793 3158 * Before proceeding, make sure that the PCIe block does not have
2794 3159 * transactions pending.
2795 3160 */
2796 - for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3161 + poll = ixgbe_pcie_timeout_poll(hw);
3162 + for (i = 0; i < poll; i++) {
2797 3163 usec_delay(100);
2798 - if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2799 - IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3164 + value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3165 + if (IXGBE_REMOVED(hw->hw_addr))
2800 3166 goto out;
3167 + if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3168 + goto out;
2801 3169 }
2802 3170
2803 - DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
3171 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
3172 + "PCIe transaction pending bit also did not clear.\n");
2804 3173 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2805 3174
2806 3175 out:
2807 3176 return status;
2808 3177 }
2809 3178
2810 3179 /**
2811 3180 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2812 3181 * @hw: pointer to hardware structure
2813 3182 * @mask: Mask to specify which semaphore to acquire
2814 3183 *
2815 3184 * Acquires the SWFW semaphore through the GSSR register for the specified
2816 3185 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2817 3186 **/
2818 -s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3187 +s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2819 3188 {
2820 - u32 gssr;
3189 + u32 gssr = 0;
2821 3190 u32 swmask = mask;
2822 3191 u32 fwmask = mask << 5;
2823 - s32 timeout = 200;
3192 + u32 timeout = 200;
3193 + u32 i;
2824 3194
2825 3195 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2826 3196
2827 - while (timeout) {
3197 + for (i = 0; i < timeout; i++) {
2828 3198 /*
2829 - * SW EEPROM semaphore bit is used for access to all
2830 - * SW_FW_SYNC/GSSR bits (not just EEPROM)
3199 + * SW NVM semaphore bit is used for access to all
3200 + * SW_FW_SYNC bits (not just NVM)
2831 3201 */
2832 3202 if (ixgbe_get_eeprom_semaphore(hw))
2833 3203 return IXGBE_ERR_SWFW_SYNC;
2834 3204
2835 3205 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2836 - if (!(gssr & (fwmask | swmask)))
2837 - break;
2838 -
2839 - /*
2840 - * Firmware currently using resource (fwmask) or other software
2841 - * thread currently using resource (swmask)
2842 - */
2843 - ixgbe_release_eeprom_semaphore(hw);
2844 - msec_delay(5);
2845 - timeout--;
3206 + if (!(gssr & (fwmask | swmask))) {
3207 + gssr |= swmask;
3208 + IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3209 + ixgbe_release_eeprom_semaphore(hw);
3210 + return IXGBE_SUCCESS;
3211 + } else {
3212 + /* Resource is currently in use by FW or SW */
3213 + ixgbe_release_eeprom_semaphore(hw);
3214 + msec_delay(5);
3215 + }
2846 3216 }
2847 3217
2848 - if (!timeout) {
2849 - DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2850 - return IXGBE_ERR_SWFW_SYNC;
2851 - }
3218 + /* If time expired clear the bits holding the lock and retry */
3219 + if (gssr & (fwmask | swmask))
3220 + ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2852 3221
2853 - gssr |= swmask;
2854 - IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2855 -
2856 - ixgbe_release_eeprom_semaphore(hw);
2857 - return IXGBE_SUCCESS;
3222 + msec_delay(5);
3223 + return IXGBE_ERR_SWFW_SYNC;
2858 3224 }
2859 3225
2860 3226 /**
2861 3227 * ixgbe_release_swfw_sync - Release SWFW semaphore
2862 3228 * @hw: pointer to hardware structure
2863 3229 * @mask: Mask to specify which semaphore to release
2864 3230 *
2865 3231 * Releases the SWFW semaphore through the GSSR register for the specified
2866 3232 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2867 3233 **/
2868 -void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3234 +void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2869 3235 {
2870 3236 u32 gssr;
2871 3237 u32 swmask = mask;
2872 3238
2873 3239 DEBUGFUNC("ixgbe_release_swfw_sync");
2874 3240
2875 - (void) ixgbe_get_eeprom_semaphore(hw);
3241 + ixgbe_get_eeprom_semaphore(hw);
2876 3242
2877 3243 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2878 3244 gssr &= ~swmask;
2879 3245 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2880 3246
2881 3247 ixgbe_release_eeprom_semaphore(hw);
2882 3248 }
2883 3249
2884 3250 /**
2885 3251 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2886 3252 * @hw: pointer to hardware structure
2887 3253 *
2888 3254 * Stops the receive data path and waits for the HW to internally empty
2889 3255 * the Rx security block
2890 3256 **/
2891 3257 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2892 3258 {
2893 3259 #define IXGBE_MAX_SECRX_POLL 40
2894 3260
2895 3261 int i;
2896 3262 int secrxreg;
2897 3263
2898 3264 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
2899 3265
2900 3266
2901 3267 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2902 3268 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2903 3269 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2904 3270 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2905 3271 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2906 3272 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2907 3273 break;
2908 3274 else
2909 3275 /* Use interrupt-safe sleep just in case */
2910 3276 usec_delay(1000);
2911 3277 }
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2912 3278
2913 3279 /* For informational purposes only */
2914 3280 if (i >= IXGBE_MAX_SECRX_POLL)
2915 3281 DEBUGOUT("Rx unit being enabled before security "
2916 3282 "path fully disabled. Continuing with init.\n");
2917 3283
2918 3284 return IXGBE_SUCCESS;
2919 3285 }
2920 3286
2921 3287 /**
3288 + * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3289 + * @hw: pointer to hardware structure
3290 + * @reg_val: Value we read from AUTOC
3291 + *
3292 + * The default case requires no protection so just to the register read.
3293 + */
3294 +s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3295 +{
3296 + *locked = FALSE;
3297 + *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3298 + return IXGBE_SUCCESS;
3299 +}
3300 +
3301 +/**
3302 + * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3303 + * @hw: pointer to hardware structure
3304 + * @reg_val: value to write to AUTOC
3305 + * @locked: bool to indicate whether the SW/FW lock was already taken by
3306 + * previous read.
3307 + *
3308 + * The default case requires no protection so just to the register write.
3309 + */
3310 +s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3311 +{
3312 + UNREFERENCED_1PARAMETER(locked);
3313 +
3314 + IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3315 + return IXGBE_SUCCESS;
3316 +}
3317 +
3318 +/**
2922 3319 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2923 3320 * @hw: pointer to hardware structure
2924 3321 *
2925 3322 * Enables the receive data path.
2926 3323 **/
2927 3324 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2928 3325 {
2929 3326 int secrxreg;
2930 3327
2931 3328 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
2932 3329
2933 3330 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2934 3331 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2935 3332 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2936 3333 IXGBE_WRITE_FLUSH(hw);
2937 3334
2938 3335 return IXGBE_SUCCESS;
2939 3336 }
2940 3337
2941 3338 /**
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2942 3339 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2943 3340 * @hw: pointer to hardware structure
2944 3341 * @regval: register value to write to RXCTRL
2945 3342 *
2946 3343 * Enables the Rx DMA unit
2947 3344 **/
2948 3345 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2949 3346 {
2950 3347 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2951 3348
2952 - IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
3349 + if (regval & IXGBE_RXCTRL_RXEN)
3350 + ixgbe_enable_rx(hw);
3351 + else
3352 + ixgbe_disable_rx(hw);
2953 3353
2954 3354 return IXGBE_SUCCESS;
2955 3355 }
2956 3356
2957 3357 /**
2958 3358 * ixgbe_blink_led_start_generic - Blink LED based on index.
2959 3359 * @hw: pointer to hardware structure
2960 3360 * @index: led number to blink
2961 3361 **/
2962 3362 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2963 3363 {
2964 3364 ixgbe_link_speed speed = 0;
2965 3365 bool link_up = 0;
2966 - u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3366 + u32 autoc_reg = 0;
2967 3367 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3368 + s32 ret_val = IXGBE_SUCCESS;
3369 + bool locked = FALSE;
2968 3370
2969 3371 DEBUGFUNC("ixgbe_blink_led_start_generic");
2970 3372
2971 3373 /*
2972 3374 * Link must be up to auto-blink the LEDs;
2973 3375 * Force it if link is down.
2974 3376 */
2975 3377 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2976 3378
2977 3379 if (!link_up) {
3380 + ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3381 + if (ret_val != IXGBE_SUCCESS)
3382 + goto out;
3383 +
2978 3384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979 3385 autoc_reg |= IXGBE_AUTOC_FLU;
2980 - IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3386 +
3387 + ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3388 + if (ret_val != IXGBE_SUCCESS)
3389 + goto out;
3390 +
2981 3391 IXGBE_WRITE_FLUSH(hw);
2982 3392 msec_delay(10);
2983 3393 }
2984 3394
2985 3395 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2986 3396 led_reg |= IXGBE_LED_BLINK(index);
2987 3397 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988 3398 IXGBE_WRITE_FLUSH(hw);
2989 3399
2990 - return IXGBE_SUCCESS;
3400 +out:
3401 + return ret_val;
2991 3402 }
2992 3403
2993 3404 /**
2994 3405 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2995 3406 * @hw: pointer to hardware structure
2996 3407 * @index: led number to stop blinking
2997 3408 **/
2998 3409 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2999 3410 {
3000 - u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3411 + u32 autoc_reg = 0;
3001 3412 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3413 + s32 ret_val = IXGBE_SUCCESS;
3414 + bool locked = FALSE;
3002 3415
3003 3416 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3004 3417
3418 + ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3419 + if (ret_val != IXGBE_SUCCESS)
3420 + goto out;
3005 3421
3006 3422 autoc_reg &= ~IXGBE_AUTOC_FLU;
3007 3423 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008 - IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3009 3424
3425 + ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3426 + if (ret_val != IXGBE_SUCCESS)
3427 + goto out;
3428 +
3010 3429 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011 3430 led_reg &= ~IXGBE_LED_BLINK(index);
3012 3431 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013 3432 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014 3433 IXGBE_WRITE_FLUSH(hw);
3015 3434
3016 - return IXGBE_SUCCESS;
3435 +out:
3436 + return ret_val;
3017 3437 }
3018 3438
3019 3439 /**
3020 3440 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3021 3441 * @hw: pointer to hardware structure
3022 3442 * @san_mac_offset: SAN MAC address offset
3023 3443 *
3024 3444 * This function will read the EEPROM location for the SAN MAC address
3025 3445 * pointer, and returns the value at that location. This is used in both
3026 3446 * get and set mac_addr routines.
3027 3447 **/
3028 3448 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3029 3449 u16 *san_mac_offset)
3030 3450 {
3451 + s32 ret_val;
3452 +
3031 3453 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3032 3454
3033 3455 /*
3034 3456 * First read the EEPROM pointer to see if the MAC addresses are
3035 3457 * available.
3036 3458 */
3037 - hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
3459 + ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3460 + san_mac_offset);
3461 + if (ret_val) {
3462 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3463 + "eeprom at offset %d failed",
3464 + IXGBE_SAN_MAC_ADDR_PTR);
3465 + }
3038 3466
3039 - return IXGBE_SUCCESS;
3467 + return ret_val;
3040 3468 }
3041 3469
3042 3470 /**
3043 3471 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3044 3472 * @hw: pointer to hardware structure
3045 3473 * @san_mac_addr: SAN MAC address
3046 3474 *
3047 3475 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3048 3476 * per-port, so set_lan_id() must be called before reading the addresses.
3049 3477 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3050 3478 * upon for non-SFP connections, so we must call it here.
3051 3479 **/
3052 3480 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3053 3481 {
3054 3482 u16 san_mac_data, san_mac_offset;
3055 3483 u8 i;
3484 + s32 ret_val;
3056 3485
3057 3486 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3058 3487
3059 3488 /*
3060 3489 * First read the EEPROM pointer to see if the MAC addresses are
3061 3490 * available. If they're not, no point in calling set_lan_id() here.
3062 3491 */
3063 - (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3064 -
3065 - if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3066 - /*
3067 - * No addresses available in this EEPROM. It's not an
3068 - * error though, so just wipe the local address and return.
3069 - */
3070 - for (i = 0; i < 6; i++)
3071 - san_mac_addr[i] = 0xFF;
3072 -
3492 + ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3493 + if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3073 3494 goto san_mac_addr_out;
3074 - }
3075 3495
3076 3496 /* make sure we know which port we need to program */
3077 3497 hw->mac.ops.set_lan_id(hw);
3078 3498 /* apply the port offset to the address offset */
3079 3499 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3080 3500 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3081 3501 for (i = 0; i < 3; i++) {
3082 - hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
3502 + ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3503 + &san_mac_data);
3504 + if (ret_val) {
3505 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3506 + "eeprom read at offset %d failed",
3507 + san_mac_offset);
3508 + goto san_mac_addr_out;
3509 + }
3083 3510 san_mac_addr[i * 2] = (u8)(san_mac_data);
3084 3511 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3085 3512 san_mac_offset++;
3086 3513 }
3514 + return IXGBE_SUCCESS;
3087 3515
3088 3516 san_mac_addr_out:
3517 + /*
3518 + * No addresses available in this EEPROM. It's not an
3519 + * error though, so just wipe the local address and return.
3520 + */
3521 + for (i = 0; i < 6; i++)
3522 + san_mac_addr[i] = 0xFF;
3089 3523 return IXGBE_SUCCESS;
3090 3524 }
3091 3525
3092 3526 /**
3093 3527 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3094 3528 * @hw: pointer to hardware structure
3095 3529 * @san_mac_addr: SAN MAC address
3096 3530 *
3097 3531 * Write a SAN MAC address to the EEPROM.
3098 3532 **/
3099 3533 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3100 3534 {
3101 - s32 status = IXGBE_SUCCESS;
3535 + s32 ret_val;
3102 3536 u16 san_mac_data, san_mac_offset;
3103 3537 u8 i;
3104 3538
3105 3539 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3106 3540
3107 3541 /* Look for SAN mac address pointer. If not defined, return */
3108 - (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3542 + ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3543 + if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3544 + return IXGBE_ERR_NO_SAN_ADDR_PTR;
3109 3545
3110 - if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3111 - status = IXGBE_ERR_NO_SAN_ADDR_PTR;
3112 - goto san_mac_addr_out;
3113 - }
3114 -
3115 3546 /* Make sure we know which port we need to write */
3116 3547 hw->mac.ops.set_lan_id(hw);
3117 3548 /* Apply the port offset to the address offset */
3118 3549 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3119 3550 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3120 3551
3121 3552 for (i = 0; i < 3; i++) {
3122 3553 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3123 3554 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3124 3555 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3125 3556 san_mac_offset++;
3126 3557 }
3127 3558
3128 -san_mac_addr_out:
3129 - return status;
3559 + return IXGBE_SUCCESS;
3130 3560 }
3131 3561
3132 3562 /**
3133 3563 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3134 3564 * @hw: pointer to hardware structure
3135 3565 *
3136 3566 * Read PCIe configuration space, and get the MSI-X vector count from
3137 3567 * the capabilities table.
3138 3568 **/
3139 3569 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3140 3570 {
3141 3571 u16 msix_count = 1;
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
3142 3572 u16 max_msix_count;
3143 3573 u16 pcie_offset;
3144 3574
3145 3575 switch (hw->mac.type) {
3146 3576 case ixgbe_mac_82598EB:
3147 3577 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3148 3578 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3149 3579 break;
3150 3580 case ixgbe_mac_82599EB:
3151 3581 case ixgbe_mac_X540:
3582 + case ixgbe_mac_X550:
3583 + case ixgbe_mac_X550EM_x:
3152 3584 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3153 3585 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3154 3586 break;
3155 3587 default:
3156 3588 return msix_count;
3157 3589 }
3158 3590
3159 3591 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3160 3592 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3593 + if (IXGBE_REMOVED(hw->hw_addr))
3594 + msix_count = 0;
3161 3595 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3162 3596
3163 3597 /* MSI-X count is zero-based in HW */
3164 3598 msix_count++;
3165 3599
3166 3600 if (msix_count > max_msix_count)
3167 3601 msix_count = max_msix_count;
3168 3602
3169 3603 return msix_count;
3170 3604 }
3171 3605
3172 3606 /**
3173 3607 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3174 3608 * @hw: pointer to hardware structure
3175 3609 * @addr: Address to put into receive address register
3176 3610 * @vmdq: VMDq pool to assign
3177 3611 *
3178 3612 * Puts an ethernet address into a receive address register, or
3179 - * finds the rar that it is aleady in; adds to the pool list
3613 + * finds the rar that it is already in; adds to the pool list
3180 3614 **/
3181 3615 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3182 3616 {
3183 3617 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3184 3618 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3185 3619 u32 rar;
3186 3620 u32 rar_low, rar_high;
3187 3621 u32 addr_low, addr_high;
3188 3622
3189 3623 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3190 3624
3191 3625 /* swap bytes for HW little endian */
3192 3626 addr_low = addr[0] | (addr[1] << 8)
3193 3627 | (addr[2] << 16)
3194 3628 | (addr[3] << 24);
3195 3629 addr_high = addr[4] | (addr[5] << 8);
3196 3630
3197 3631 /*
3198 3632 * Either find the mac_id in rar or find the first empty space.
3199 3633 * rar_highwater points to just after the highest currently used
3200 3634 * rar in order to shorten the search. It grows when we add a new
3201 3635 * rar to the top.
3202 3636 */
3203 3637 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3204 3638 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3205 3639
3206 3640 if (((IXGBE_RAH_AV & rar_high) == 0)
3207 3641 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
↓ open down ↓ |
18 lines elided |
↑ open up ↑ |
3208 3642 first_empty_rar = rar;
3209 3643 } else if ((rar_high & 0xFFFF) == addr_high) {
3210 3644 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3211 3645 if (rar_low == addr_low)
3212 3646 break; /* found it already in the rars */
3213 3647 }
3214 3648 }
3215 3649
3216 3650 if (rar < hw->mac.rar_highwater) {
3217 3651 /* already there so just add to the pool bits */
3218 - (void) ixgbe_set_vmdq(hw, rar, vmdq);
3652 + ixgbe_set_vmdq(hw, rar, vmdq);
3219 3653 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3220 3654 /* stick it into first empty RAR slot we found */
3221 3655 rar = first_empty_rar;
3222 - (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3656 + ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3223 3657 } else if (rar == hw->mac.rar_highwater) {
3224 3658 /* add it to the top of the list and inc the highwater mark */
3225 - (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3659 + ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3226 3660 hw->mac.rar_highwater++;
3227 3661 } else if (rar >= hw->mac.num_rar_entries) {
3228 3662 return IXGBE_ERR_INVALID_MAC_ADDR;
3229 3663 }
3230 3664
3231 3665 /*
3232 3666 * If we found rar[0], make sure the default pool bit (we use pool 0)
3233 3667 * remains cleared to be sure default pool packets will get delivered
3234 3668 */
3235 3669 if (rar == 0)
3236 - (void) ixgbe_clear_vmdq(hw, rar, 0);
3670 + ixgbe_clear_vmdq(hw, rar, 0);
3237 3671
3238 3672 return rar;
3239 3673 }
3240 3674
3241 3675 /**
3242 3676 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3243 3677 * @hw: pointer to hardware struct
3244 3678 * @rar: receive address register index to disassociate
3245 3679 * @vmdq: VMDq pool index to remove from the rar
3246 3680 **/
3247 3681 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3248 3682 {
3249 3683 u32 mpsar_lo, mpsar_hi;
3250 3684 u32 rar_entries = hw->mac.num_rar_entries;
3251 3685
3252 3686 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3253 3687
3254 3688 /* Make sure we are using a valid rar index range */
3255 3689 if (rar >= rar_entries) {
3256 - DEBUGOUT1("RAR index %d is out of range.\n", rar);
3690 + ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3691 + "RAR index %d is out of range.\n", rar);
3257 3692 return IXGBE_ERR_INVALID_ARGUMENT;
3258 3693 }
3259 3694
3260 3695 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3261 3696 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3262 3697
3698 + if (IXGBE_REMOVED(hw->hw_addr))
3699 + goto done;
3700 +
3263 3701 if (!mpsar_lo && !mpsar_hi)
3264 3702 goto done;
3265 3703
3266 3704 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3267 3705 if (mpsar_lo) {
3268 3706 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3269 3707 mpsar_lo = 0;
3270 3708 }
3271 3709 if (mpsar_hi) {
3272 3710 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3273 3711 mpsar_hi = 0;
3274 3712 }
3275 3713 } else if (vmdq < 32) {
3276 3714 mpsar_lo &= ~(1 << vmdq);
3277 3715 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3278 3716 } else {
3279 3717 mpsar_hi &= ~(1 << (vmdq - 32));
3280 3718 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3281 3719 }
3282 3720
3283 3721 /* was that the last pool using this rar? */
3284 3722 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3285 3723 hw->mac.ops.clear_rar(hw, rar);
3286 3724 done:
3287 3725 return IXGBE_SUCCESS;
3288 3726 }
3289 3727
3290 3728 /**
3291 3729 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3292 3730 * @hw: pointer to hardware struct
3293 3731 * @rar: receive address register index to associate with a VMDq index
3294 3732 * @vmdq: VMDq pool index
↓ open down ↓ |
22 lines elided |
↑ open up ↑ |
3295 3733 **/
3296 3734 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3297 3735 {
3298 3736 u32 mpsar;
3299 3737 u32 rar_entries = hw->mac.num_rar_entries;
3300 3738
3301 3739 DEBUGFUNC("ixgbe_set_vmdq_generic");
3302 3740
3303 3741 /* Make sure we are using a valid rar index range */
3304 3742 if (rar >= rar_entries) {
3305 - DEBUGOUT1("RAR index %d is out of range.\n", rar);
3743 + ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3744 + "RAR index %d is out of range.\n", rar);
3306 3745 return IXGBE_ERR_INVALID_ARGUMENT;
3307 3746 }
3308 3747
3309 3748 if (vmdq < 32) {
3310 3749 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3311 3750 mpsar |= 1 << vmdq;
3312 3751 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3313 3752 } else {
3314 3753 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3315 3754 mpsar |= 1 << (vmdq - 32);
3316 3755 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3317 3756 }
3318 3757 return IXGBE_SUCCESS;
3319 3758 }
3320 3759
3321 3760 /**
3322 3761 * This function should only be involved in the IOV mode.
3323 3762 * In IOV mode, Default pool is next pool after the number of
3324 3763 * VFs advertized and not 0.
3325 3764 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3326 3765 *
3327 3766 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3328 3767 * @hw: pointer to hardware struct
3329 3768 * @vmdq: VMDq pool index
3330 3769 **/
3331 3770 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3332 3771 {
3333 3772 u32 rar = hw->mac.san_mac_rar_index;
3334 3773
3335 3774 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3336 3775
3337 3776 if (vmdq < 32) {
3338 3777 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3339 3778 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3340 3779 } else {
3341 3780 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3342 3781 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3343 3782 }
3344 3783
3345 3784 return IXGBE_SUCCESS;
3346 3785 }
3347 3786
3348 3787 /**
3349 3788 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3350 3789 * @hw: pointer to hardware structure
3351 3790 **/
3352 3791 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3353 3792 {
3354 3793 int i;
3355 3794
3356 3795 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3357 3796 DEBUGOUT(" Clearing UTA\n");
3358 3797
3359 3798 for (i = 0; i < 128; i++)
3360 3799 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3361 3800
3362 3801 return IXGBE_SUCCESS;
3363 3802 }
3364 3803
3365 3804 /**
3366 3805 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3367 3806 * @hw: pointer to hardware structure
3368 3807 * @vlan: VLAN id to write to VLAN filter
3369 3808 *
3370 3809 * return the VLVF index where this VLAN id should be placed
3371 3810 *
3372 3811 **/
3373 3812 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3374 3813 {
3375 3814 u32 bits = 0;
3376 3815 u32 first_empty_slot = 0;
3377 3816 s32 regindex;
3378 3817
3379 3818 /* short cut the special case */
3380 3819 if (vlan == 0)
3381 3820 return 0;
3382 3821
3383 3822 /*
3384 3823 * Search for the vlan id in the VLVF entries. Save off the first empty
3385 3824 * slot found along the way
3386 3825 */
3387 3826 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3388 3827 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3389 3828 if (!bits && !(first_empty_slot))
3390 3829 first_empty_slot = regindex;
3391 3830 else if ((bits & 0x0FFF) == vlan)
3392 3831 break;
3393 3832 }
↓ open down ↓ |
78 lines elided |
↑ open up ↑ |
3394 3833
3395 3834 /*
3396 3835 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3397 3836 * in the VLVF. Else use the first empty VLVF register for this
3398 3837 * vlan id.
3399 3838 */
3400 3839 if (regindex >= IXGBE_VLVF_ENTRIES) {
3401 3840 if (first_empty_slot)
3402 3841 regindex = first_empty_slot;
3403 3842 else {
3404 - DEBUGOUT("No space in VLVF.\n");
3843 + ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3844 + "No space in VLVF.\n");
3405 3845 regindex = IXGBE_ERR_NO_SPACE;
3406 3846 }
3407 3847 }
3408 3848
3409 3849 return regindex;
3410 3850 }
3411 3851
3412 3852 /**
3413 3853 * ixgbe_set_vfta_generic - Set VLAN filter table
3414 3854 * @hw: pointer to hardware structure
3415 3855 * @vlan: VLAN id to write to VLAN filter
3416 3856 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3417 3857 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3418 3858 *
3419 3859 * Turn on/off specified VLAN in the VLAN filter table.
3420 3860 **/
3421 3861 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3422 3862 bool vlan_on)
3423 3863 {
3424 3864 s32 regindex;
3425 3865 u32 bitindex;
3426 3866 u32 vfta;
3427 3867 u32 targetbit;
3428 3868 s32 ret_val = IXGBE_SUCCESS;
3429 3869 bool vfta_changed = FALSE;
3430 3870
3431 3871 DEBUGFUNC("ixgbe_set_vfta_generic");
3432 3872
3433 3873 if (vlan > 4095)
3434 3874 return IXGBE_ERR_PARAM;
3435 3875
3436 3876 /*
3437 3877 * this is a 2 part operation - first the VFTA, then the
3438 3878 * VLVF and VLVFB if VT Mode is set
3439 3879 * We don't write the VFTA until we know the VLVF part succeeded.
3440 3880 */
3441 3881
3442 3882 /* Part 1
3443 3883 * The VFTA is a bitstring made up of 128 32-bit registers
3444 3884 * that enable the particular VLAN id, much like the MTA:
3445 3885 * bits[11-5]: which register
3446 3886 * bits[4-0]: which bit in the register
3447 3887 */
3448 3888 regindex = (vlan >> 5) & 0x7F;
3449 3889 bitindex = vlan & 0x1F;
3450 3890 targetbit = (1 << bitindex);
3451 3891 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3452 3892
3453 3893 if (vlan_on) {
3454 3894 if (!(vfta & targetbit)) {
3455 3895 vfta |= targetbit;
3456 3896 vfta_changed = TRUE;
3457 3897 }
3458 3898 } else {
3459 3899 if ((vfta & targetbit)) {
3460 3900 vfta &= ~targetbit;
3461 3901 vfta_changed = TRUE;
3462 3902 }
3463 3903 }
3464 3904
3465 3905 /* Part 2
3466 3906 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3467 3907 */
3468 3908 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3469 3909 &vfta_changed);
3470 3910 if (ret_val != IXGBE_SUCCESS)
3471 3911 return ret_val;
3472 3912
3473 3913 if (vfta_changed)
3474 3914 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3475 3915
3476 3916 return IXGBE_SUCCESS;
3477 3917 }
3478 3918
3479 3919 /**
3480 3920 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3481 3921 * @hw: pointer to hardware structure
3482 3922 * @vlan: VLAN id to write to VLAN filter
3483 3923 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3484 3924 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3485 3925 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3486 3926 * should be changed
3487 3927 *
3488 3928 * Turn on/off specified bit in VLVF table.
3489 3929 **/
3490 3930 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3491 3931 bool vlan_on, bool *vfta_changed)
3492 3932 {
3493 3933 u32 vt;
3494 3934
3495 3935 DEBUGFUNC("ixgbe_set_vlvf_generic");
3496 3936
3497 3937 if (vlan > 4095)
3498 3938 return IXGBE_ERR_PARAM;
3499 3939
3500 3940 /* If VT Mode is set
3501 3941 * Either vlan_on
3502 3942 * make sure the vlan is in VLVF
3503 3943 * set the vind bit in the matching VLVFB
3504 3944 * Or !vlan_on
3505 3945 * clear the pool bit and possibly the vind
3506 3946 */
3507 3947 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3508 3948 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3509 3949 s32 vlvf_index;
3510 3950 u32 bits;
3511 3951
3512 3952 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3513 3953 if (vlvf_index < 0)
3514 3954 return vlvf_index;
3515 3955
3516 3956 if (vlan_on) {
3517 3957 /* set the pool bit */
3518 3958 if (vind < 32) {
3519 3959 bits = IXGBE_READ_REG(hw,
3520 3960 IXGBE_VLVFB(vlvf_index * 2));
3521 3961 bits |= (1 << vind);
3522 3962 IXGBE_WRITE_REG(hw,
3523 3963 IXGBE_VLVFB(vlvf_index * 2),
3524 3964 bits);
3525 3965 } else {
3526 3966 bits = IXGBE_READ_REG(hw,
3527 3967 IXGBE_VLVFB((vlvf_index * 2) + 1));
3528 3968 bits |= (1 << (vind - 32));
3529 3969 IXGBE_WRITE_REG(hw,
3530 3970 IXGBE_VLVFB((vlvf_index * 2) + 1),
3531 3971 bits);
3532 3972 }
3533 3973 } else {
3534 3974 /* clear the pool bit */
3535 3975 if (vind < 32) {
3536 3976 bits = IXGBE_READ_REG(hw,
3537 3977 IXGBE_VLVFB(vlvf_index * 2));
3538 3978 bits &= ~(1 << vind);
3539 3979 IXGBE_WRITE_REG(hw,
3540 3980 IXGBE_VLVFB(vlvf_index * 2),
3541 3981 bits);
3542 3982 bits |= IXGBE_READ_REG(hw,
3543 3983 IXGBE_VLVFB((vlvf_index * 2) + 1));
3544 3984 } else {
3545 3985 bits = IXGBE_READ_REG(hw,
3546 3986 IXGBE_VLVFB((vlvf_index * 2) + 1));
3547 3987 bits &= ~(1 << (vind - 32));
3548 3988 IXGBE_WRITE_REG(hw,
3549 3989 IXGBE_VLVFB((vlvf_index * 2) + 1),
3550 3990 bits);
3551 3991 bits |= IXGBE_READ_REG(hw,
3552 3992 IXGBE_VLVFB(vlvf_index * 2));
3553 3993 }
3554 3994 }
3555 3995
3556 3996 /*
3557 3997 * If there are still bits set in the VLVFB registers
3558 3998 * for the VLAN ID indicated we need to see if the
3559 3999 * caller is requesting that we clear the VFTA entry bit.
3560 4000 * If the caller has requested that we clear the VFTA
3561 4001 * entry bit but there are still pools/VFs using this VLAN
3562 4002 * ID entry then ignore the request. We're not worried
3563 4003 * about the case where we're turning the VFTA VLAN ID
3564 4004 * entry bit on, only when requested to turn it off as
3565 4005 * there may be multiple pools and/or VFs using the
3566 4006 * VLAN ID entry. In that case we cannot clear the
3567 4007 * VFTA bit until all pools/VFs using that VLAN ID have also
3568 4008 * been cleared. This will be indicated by "bits" being
3569 4009 * zero.
3570 4010 */
3571 4011 if (bits) {
3572 4012 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3573 4013 (IXGBE_VLVF_VIEN | vlan));
3574 4014 if ((!vlan_on) && (vfta_changed != NULL)) {
3575 4015 /* someone wants to clear the vfta entry
3576 4016 * but some pools/VFs are still using it.
3577 4017 * Ignore it. */
3578 4018 *vfta_changed = FALSE;
3579 4019 }
3580 4020 } else
3581 4021 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3582 4022 }
3583 4023
3584 4024 return IXGBE_SUCCESS;
3585 4025 }
3586 4026
3587 4027 /**
3588 4028 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3589 4029 * @hw: pointer to hardware structure
3590 4030 *
3591 4031 * Clears the VLAN filer table, and the VMDq index associated with the filter
3592 4032 **/
3593 4033 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3594 4034 {
3595 4035 u32 offset;
3596 4036
3597 4037 DEBUGFUNC("ixgbe_clear_vfta_generic");
3598 4038
3599 4039 for (offset = 0; offset < hw->mac.vft_size; offset++)
3600 4040 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3601 4041
3602 4042 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3603 4043 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3604 4044 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3605 4045 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3606 4046 }
3607 4047
3608 4048 return IXGBE_SUCCESS;
3609 4049 }
3610 4050
3611 4051 /**
3612 4052 * ixgbe_check_mac_link_generic - Determine link and speed status
3613 4053 * @hw: pointer to hardware structure
3614 4054 * @speed: pointer to link speed
3615 4055 * @link_up: TRUE when link is up
3616 4056 * @link_up_wait_to_complete: bool used to wait for link up or not
3617 4057 *
3618 4058 * Reads the links register to determine if link is up and the current speed
3619 4059 **/
3620 4060 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3621 4061 bool *link_up, bool link_up_wait_to_complete)
3622 4062 {
3623 4063 u32 links_reg, links_orig;
3624 4064 u32 i;
3625 4065
3626 4066 DEBUGFUNC("ixgbe_check_mac_link_generic");
3627 4067
3628 4068 /* clear the old state */
↓ open down ↓ |
214 lines elided |
↑ open up ↑ |
3629 4069 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3630 4070
3631 4071 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3632 4072
3633 4073 if (links_orig != links_reg) {
3634 4074 DEBUGOUT2("LINKS changed from %08X to %08X\n",
3635 4075 links_orig, links_reg);
3636 4076 }
3637 4077
3638 4078 if (link_up_wait_to_complete) {
3639 - for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4079 + for (i = 0; i < hw->mac.max_link_up_time; i++) {
3640 4080 if (links_reg & IXGBE_LINKS_UP) {
3641 4081 *link_up = TRUE;
3642 4082 break;
3643 4083 } else {
3644 4084 *link_up = FALSE;
3645 4085 }
3646 4086 msec_delay(100);
3647 4087 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3648 4088 }
3649 4089 } else {
3650 4090 if (links_reg & IXGBE_LINKS_UP)
3651 4091 *link_up = TRUE;
3652 4092 else
3653 4093 *link_up = FALSE;
3654 4094 }
3655 4095
3656 - if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3657 - IXGBE_LINKS_SPEED_10G_82599)
4096 + switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4097 + case IXGBE_LINKS_SPEED_10G_82599:
3658 4098 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3659 - else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3660 - IXGBE_LINKS_SPEED_1G_82599)
4099 + if (hw->mac.type >= ixgbe_mac_X550) {
4100 + if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4101 + *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4102 + }
4103 + break;
4104 + case IXGBE_LINKS_SPEED_1G_82599:
3661 4105 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3662 - else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3663 - IXGBE_LINKS_SPEED_100_82599)
4106 + break;
4107 + case IXGBE_LINKS_SPEED_100_82599:
3664 4108 *speed = IXGBE_LINK_SPEED_100_FULL;
3665 - else
4109 + if (hw->mac.type >= ixgbe_mac_X550) {
4110 + if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4111 + *speed = IXGBE_LINK_SPEED_5GB_FULL;
4112 + }
4113 + break;
4114 + default:
3666 4115 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4116 + }
3667 4117
3668 4118 return IXGBE_SUCCESS;
3669 4119 }
3670 4120
3671 4121 /**
3672 4122 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3673 4123 * the EEPROM
3674 4124 * @hw: pointer to hardware structure
3675 4125 * @wwnn_prefix: the alternative WWNN prefix
3676 4126 * @wwpn_prefix: the alternative WWPN prefix
3677 4127 *
3678 4128 * This function will read the EEPROM from the alternative SAN MAC address
3679 4129 * block to check the support for the alternative WWNN/WWPN prefix support.
3680 4130 **/
3681 4131 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3682 4132 u16 *wwpn_prefix)
3683 4133 {
↓ open down ↓ |
7 lines elided |
↑ open up ↑ |
3684 4134 u16 offset, caps;
3685 4135 u16 alt_san_mac_blk_offset;
3686 4136
3687 4137 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3688 4138
3689 4139 /* clear output first */
3690 4140 *wwnn_prefix = 0xFFFF;
3691 4141 *wwpn_prefix = 0xFFFF;
3692 4142
3693 4143 /* check if alternative SAN MAC is supported */
3694 - hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3695 - &alt_san_mac_blk_offset);
4144 + offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4145 + if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4146 + goto wwn_prefix_err;
3696 4147
3697 4148 if ((alt_san_mac_blk_offset == 0) ||
3698 4149 (alt_san_mac_blk_offset == 0xFFFF))
3699 4150 goto wwn_prefix_out;
3700 4151
3701 4152 /* check capability in alternative san mac address block */
3702 4153 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3703 - hw->eeprom.ops.read(hw, offset, &caps);
4154 + if (hw->eeprom.ops.read(hw, offset, &caps))
4155 + goto wwn_prefix_err;
3704 4156 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3705 4157 goto wwn_prefix_out;
3706 4158
3707 4159 /* get the corresponding prefix for WWNN/WWPN */
3708 4160 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3709 - hw->eeprom.ops.read(hw, offset, wwnn_prefix);
4161 + if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4162 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4163 + "eeprom read at offset %d failed", offset);
4164 + }
3710 4165
3711 4166 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3712 - hw->eeprom.ops.read(hw, offset, wwpn_prefix);
4167 + if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4168 + goto wwn_prefix_err;
3713 4169
3714 4170 wwn_prefix_out:
3715 4171 return IXGBE_SUCCESS;
4172 +
4173 +wwn_prefix_err:
4174 + ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4175 + "eeprom read at offset %d failed", offset);
4176 + return IXGBE_SUCCESS;
3716 4177 }
3717 4178
3718 4179 /**
3719 4180 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3720 4181 * @hw: pointer to hardware structure
3721 4182 * @bs: the fcoe boot status
3722 4183 *
3723 4184 * This function will read the FCOE boot status from the iSCSI FCOE block
3724 4185 **/
3725 4186 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3726 4187 {
3727 4188 u16 offset, caps, flags;
3728 4189 s32 status;
3729 4190
3730 4191 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
3731 4192
3732 4193 /* clear output first */
3733 4194 *bs = ixgbe_fcoe_bootstatus_unavailable;
3734 4195
3735 4196 /* check if FCOE IBA block is present */
3736 4197 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3737 4198 status = hw->eeprom.ops.read(hw, offset, &caps);
3738 4199 if (status != IXGBE_SUCCESS)
3739 4200 goto out;
3740 4201
3741 4202 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3742 4203 goto out;
3743 4204
3744 4205 /* check if iSCSI FCOE block is populated */
3745 4206 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3746 4207 if (status != IXGBE_SUCCESS)
3747 4208 goto out;
3748 4209
3749 4210 if ((offset == 0) || (offset == 0xFFFF))
3750 4211 goto out;
3751 4212
3752 4213 /* read fcoe flags in iSCSI FCOE block */
3753 4214 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3754 4215 status = hw->eeprom.ops.read(hw, offset, &flags);
3755 4216 if (status != IXGBE_SUCCESS)
3756 4217 goto out;
3757 4218
3758 4219 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3759 4220 *bs = ixgbe_fcoe_bootstatus_enabled;
3760 4221 else
3761 4222 *bs = ixgbe_fcoe_bootstatus_disabled;
3762 4223
3763 4224 out:
3764 4225 return status;
3765 4226 }
3766 4227
3767 4228 /**
3768 4229 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3769 4230 * @hw: pointer to hardware structure
3770 4231 * @enable: enable or disable switch for anti-spoofing
3771 4232 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3772 4233 *
3773 4234 **/
3774 4235 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3775 4236 {
3776 4237 int j;
3777 4238 int pf_target_reg = pf >> 3;
3778 4239 int pf_target_shift = pf % 8;
3779 4240 u32 pfvfspoof = 0;
3780 4241
3781 4242 if (hw->mac.type == ixgbe_mac_82598EB)
3782 4243 return;
3783 4244
3784 4245 if (enable)
3785 4246 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3786 4247
3787 4248 /*
3788 4249 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3789 4250 * MAC anti-spoof enables in each register array element.
3790 4251 */
3791 4252 for (j = 0; j < pf_target_reg; j++)
3792 4253 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3793 4254
3794 4255 /*
3795 4256 * The PF should be allowed to spoof so that it can support
3796 4257 * emulation mode NICs. Do not set the bits assigned to the PF
3797 4258 */
3798 4259 pfvfspoof &= (1 << pf_target_shift) - 1;
3799 4260 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3800 4261
3801 4262 /*
3802 4263 * Remaining pools belong to the PF so they do not need to have
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77 lines elided |
↑ open up ↑ |
3803 4264 * anti-spoofing enabled.
3804 4265 */
3805 4266 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3806 4267 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3807 4268 }
3808 4269
3809 4270 /**
3810 4271 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3811 4272 * @hw: pointer to hardware structure
3812 4273 * @enable: enable or disable switch for VLAN anti-spoofing
3813 - * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4274 + * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3814 4275 *
3815 4276 **/
3816 4277 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3817 4278 {
3818 4279 int vf_target_reg = vf >> 3;
3819 4280 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3820 4281 u32 pfvfspoof;
3821 4282
3822 4283 if (hw->mac.type == ixgbe_mac_82598EB)
3823 4284 return;
3824 4285
3825 4286 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3826 4287 if (enable)
3827 4288 pfvfspoof |= (1 << vf_target_shift);
3828 4289 else
3829 4290 pfvfspoof &= ~(1 << vf_target_shift);
3830 4291 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3831 4292 }
3832 4293
3833 4294 /**
3834 4295 * ixgbe_get_device_caps_generic - Get additional device capabilities
3835 4296 * @hw: pointer to hardware structure
3836 4297 * @device_caps: the EEPROM word with the extra device capabilities
3837 4298 *
3838 4299 * This function will read the EEPROM location for the device capabilities,
3839 4300 * and return the word through device_caps.
3840 4301 **/
3841 4302 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3842 4303 {
3843 4304 DEBUGFUNC("ixgbe_get_device_caps_generic");
3844 4305
3845 4306 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3846 4307
3847 4308 return IXGBE_SUCCESS;
3848 4309 }
3849 4310
3850 4311 /**
3851 4312 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
3852 4313 * @hw: pointer to hardware structure
3853 4314 *
3854 4315 **/
3855 4316 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
3856 4317 {
3857 4318 u32 regval;
3858 4319 u32 i;
3859 4320
3860 4321 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
3861 4322
3862 4323 /* Enable relaxed ordering */
3863 4324 for (i = 0; i < hw->mac.max_tx_queues; i++) {
3864 4325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
3865 4326 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3866 4327 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3867 4328 }
3868 4329
3869 4330 for (i = 0; i < hw->mac.max_rx_queues; i++) {
3870 4331 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3871 4332 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
3872 4333 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
3873 4334 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3874 4335 }
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51 lines elided |
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3875 4336
3876 4337 }
3877 4338
3878 4339 /**
3879 4340 * ixgbe_calculate_checksum - Calculate checksum for buffer
3880 4341 * @buffer: pointer to EEPROM
3881 4342 * @length: size of EEPROM to calculate a checksum for
3882 4343 * Calculates the checksum for some buffer on a specified length. The
3883 4344 * checksum calculated is returned.
3884 4345 **/
3885 -static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4346 +u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3886 4347 {
3887 4348 u32 i;
3888 4349 u8 sum = 0;
3889 4350
3890 4351 DEBUGFUNC("ixgbe_calculate_checksum");
3891 4352
3892 4353 if (!buffer)
3893 4354 return 0;
3894 4355
3895 4356 for (i = 0; i < length; i++)
3896 4357 sum += buffer[i];
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3897 4358
3898 4359 return (u8) (0 - sum);
3899 4360 }
3900 4361
3901 4362 /**
3902 4363 * ixgbe_host_interface_command - Issue command to manageability block
3903 4364 * @hw: pointer to the HW structure
3904 4365 * @buffer: contains the command to write and where the return status will
3905 4366 * be placed
3906 4367 * @length: length of buffer, must be multiple of 4 bytes
4368 + * @timeout: time in ms to wait for command completion
4369 + * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4370 + * Needed because FW structures are big endian and decoding of
4371 + * these fields can be 8 bit or 16 bit based on command. Decoding
4372 + * is not easily understood without making a table of commands.
4373 + * So we will leave this up to the caller to read back the data
4374 + * in these cases.
3907 4375 *
3908 4376 * Communicates with the manageability block. On success return IXGBE_SUCCESS
3909 4377 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3910 4378 **/
3911 -static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3912 - u32 length)
4379 +s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4380 + u32 length, u32 timeout, bool return_data)
3913 4381 {
3914 - u32 hicr, i, bi;
4382 + u32 hicr, i, bi, fwsts;
3915 4383 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3916 - u8 buf_len, dword_len;
4384 + u16 buf_len;
4385 + u16 dword_len;
3917 4386
3918 - s32 ret_val = IXGBE_SUCCESS;
3919 -
3920 4387 DEBUGFUNC("ixgbe_host_interface_command");
3921 4388
3922 - if (length == 0 || length & 0x3 ||
3923 - length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3924 - DEBUGOUT("Buffer length failure.\n");
3925 - ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3926 - goto out;
4389 + if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4390 + DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4391 + return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3927 4392 }
4393 + /* Set bit 9 of FWSTS clearing FW reset indication */
4394 + fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4395 + IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3928 4396
3929 4397 /* Check that the host interface is enabled. */
3930 4398 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3931 4399 if ((hicr & IXGBE_HICR_EN) == 0) {
3932 4400 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
3933 - ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3934 - goto out;
4401 + return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3935 4402 }
3936 4403
3937 - /* Calculate length in DWORDs */
4404 + /* Calculate length in DWORDs. We must be DWORD aligned */
4405 + if ((length % (sizeof(u32))) != 0) {
4406 + DEBUGOUT("Buffer length failure, not aligned to dword");
4407 + return IXGBE_ERR_INVALID_ARGUMENT;
4408 + }
4409 +
3938 4410 dword_len = length >> 2;
3939 4411
3940 - /*
3941 - * The device driver writes the relevant command block
4412 + /* The device driver writes the relevant command block
3942 4413 * into the ram area.
3943 4414 */
3944 4415 for (i = 0; i < dword_len; i++)
3945 4416 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3946 4417 i, IXGBE_CPU_TO_LE32(buffer[i]));
3947 4418
3948 4419 /* Setting this bit tells the ARC that a new command is pending. */
3949 4420 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3950 4421
3951 - for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4422 + for (i = 0; i < timeout; i++) {
3952 4423 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3953 4424 if (!(hicr & IXGBE_HICR_C))
3954 4425 break;
3955 4426 msec_delay(1);
3956 4427 }
3957 4428
3958 - /* Check command successful completion. */
3959 - if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3960 - (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3961 - DEBUGOUT("Command has failed with no status valid.\n");
3962 - ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3963 - goto out;
4429 + /* Check command completion */
4430 + if ((timeout != 0 && i == timeout) ||
4431 + !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4432 + ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4433 + "Command has failed with no status valid.\n");
4434 + return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3964 4435 }
3965 4436
4437 + if (!return_data)
4438 + return 0;
4439 +
3966 4440 /* Calculate length in DWORDs */
3967 4441 dword_len = hdr_size >> 2;
3968 4442
3969 4443 /* first pull in the header so we know the buffer length */
3970 4444 for (bi = 0; bi < dword_len; bi++) {
3971 4445 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3972 - buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
4446 + IXGBE_LE32_TO_CPUS(&buffer[bi]);
3973 4447 }
3974 4448
3975 4449 /* If there is any thing in data position pull it in */
3976 4450 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3977 4451 if (buf_len == 0)
3978 - goto out;
4452 + return 0;
3979 4453
3980 - if (length < (buf_len + hdr_size)) {
4454 + if (length < buf_len + hdr_size) {
3981 4455 DEBUGOUT("Buffer not large enough for reply message.\n");
3982 - ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3983 - goto out;
4456 + return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3984 4457 }
3985 4458
3986 4459 /* Calculate length in DWORDs, add 3 for odd lengths */
3987 4460 dword_len = (buf_len + 3) >> 2;
3988 4461
3989 - /* Pull in the rest of the buffer (bi is where we left off)*/
4462 + /* Pull in the rest of the buffer (bi is where we left off) */
3990 4463 for (; bi <= dword_len; bi++) {
3991 4464 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3992 - buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
4465 + IXGBE_LE32_TO_CPUS(&buffer[bi]);
3993 4466 }
3994 4467
3995 -out:
3996 - return ret_val;
4468 + return 0;
3997 4469 }
3998 4470
3999 4471 /**
4000 4472 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4001 4473 * @hw: pointer to the HW structure
4002 4474 * @maj: driver version major number
4003 4475 * @min: driver version minor number
4004 4476 * @build: driver version build number
4005 4477 * @sub: driver version sub build number
4006 4478 *
4007 4479 * Sends driver version number to firmware through the manageability
4008 4480 * block. On success return IXGBE_SUCCESS
4009 4481 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4010 4482 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4011 4483 **/
4012 4484 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4013 4485 u8 build, u8 sub)
4014 4486 {
4015 4487 struct ixgbe_hic_drv_info fw_cmd;
4016 4488 int i;
4017 4489 s32 ret_val = IXGBE_SUCCESS;
4018 4490
4019 4491 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4020 4492
4021 4493 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4022 4494 != IXGBE_SUCCESS) {
4023 4495 ret_val = IXGBE_ERR_SWFW_SYNC;
4024 4496 goto out;
4025 4497 }
4026 4498
4027 4499 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4028 4500 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4029 4501 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4030 4502 fw_cmd.port_num = (u8)hw->bus.func;
4031 4503 fw_cmd.ver_maj = maj;
↓ open down ↓ |
25 lines elided |
↑ open up ↑ |
4032 4504 fw_cmd.ver_min = min;
4033 4505 fw_cmd.ver_build = build;
4034 4506 fw_cmd.ver_sub = sub;
4035 4507 fw_cmd.hdr.checksum = 0;
4036 4508 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4037 4509 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4038 4510 fw_cmd.pad = 0;
4039 4511 fw_cmd.pad2 = 0;
4040 4512
4041 4513 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4042 - /* LINTED */
4043 4514 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4044 - sizeof(fw_cmd));
4515 + sizeof(fw_cmd),
4516 + IXGBE_HI_COMMAND_TIMEOUT,
4517 + TRUE);
4045 4518 if (ret_val != IXGBE_SUCCESS)
4046 4519 continue;
4047 4520
4048 4521 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4049 4522 FW_CEM_RESP_STATUS_SUCCESS)
4050 4523 ret_val = IXGBE_SUCCESS;
4051 4524 else
4052 4525 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4053 4526
4054 4527 break;
4055 4528 }
4056 4529
4057 4530 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4058 4531 out:
4059 4532 return ret_val;
4060 4533 }
4061 4534
4062 4535 /**
4063 4536 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4064 4537 * @hw: pointer to hardware structure
4065 4538 * @num_pb: number of packet buffers to allocate
4066 4539 * @headroom: reserve n KB of headroom
4067 4540 * @strategy: packet buffer allocation strategy
4068 4541 **/
4069 4542 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4070 4543 int strategy)
4071 4544 {
4072 4545 u32 pbsize = hw->mac.rx_pb_size;
4073 4546 int i = 0;
4074 4547 u32 rxpktsize, txpktsize, txpbthresh;
4075 4548
4076 4549 /* Reserve headroom */
4077 4550 pbsize -= headroom;
4078 4551
4079 4552 if (!num_pb)
4080 4553 num_pb = 1;
4081 4554
4082 4555 /* Divide remaining packet buffer space amongst the number of packet
4083 4556 * buffers requested using supplied strategy.
4084 4557 */
4085 4558 switch (strategy) {
↓ open down ↓ |
31 lines elided |
↑ open up ↑ |
4086 4559 case PBA_STRATEGY_WEIGHTED:
4087 4560 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4088 4561 * buffer with 5/8 of the packet buffer space.
4089 4562 */
4090 4563 rxpktsize = (pbsize * 5) / (num_pb * 4);
4091 4564 pbsize -= rxpktsize * (num_pb / 2);
4092 4565 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4093 4566 for (; i < (num_pb / 2); i++)
4094 4567 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4095 4568 /* Fall through to configure remaining packet buffers */
4096 - /* FALLTHRU */
4097 4569 case PBA_STRATEGY_EQUAL:
4098 4570 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4099 4571 for (; i < num_pb; i++)
4100 4572 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4101 4573 break;
4102 4574 default:
4103 4575 break;
4104 4576 }
4105 4577
4106 4578 /* Only support an equally distributed Tx packet buffer strategy. */
4107 4579 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4108 4580 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4109 4581 for (i = 0; i < num_pb; i++) {
4110 4582 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4111 4583 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4112 4584 }
4113 4585
4114 4586 /* Clear unused TCs, if any, to zero buffer size*/
4115 4587 for (; i < IXGBE_MAX_PB; i++) {
4116 4588 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4117 4589 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4118 4590 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4119 4591 }
4120 4592 }
4121 4593
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↑ open up ↑ |
4122 4594 /**
4123 4595 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4124 4596 * @hw: pointer to the hardware structure
4125 4597 *
4126 4598 * The 82599 and x540 MACs can experience issues if TX work is still pending
4127 4599 * when a reset occurs. This function prevents this by flushing the PCIe
4128 4600 * buffers on the system.
4129 4601 **/
4130 4602 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4131 4603 {
4132 - u32 gcr_ext, hlreg0;
4604 + u32 gcr_ext, hlreg0, i, poll;
4605 + u16 value;
4133 4606
4134 4607 /*
4135 4608 * If double reset is not requested then all transactions should
4136 4609 * already be clear and as such there is no work to do
4137 4610 */
4138 4611 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4139 4612 return;
4140 4613
4141 4614 /*
4142 4615 * Set loopback enable to prevent any transmits from being sent
4143 4616 * should the link come up. This assumes that the RXCTRL.RXEN bit
4144 4617 * has already been cleared.
4145 4618 */
4146 4619 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4147 4620 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4148 4621
4622 + /* Wait for a last completion before clearing buffers */
4623 + IXGBE_WRITE_FLUSH(hw);
4624 + msec_delay(3);
4625 +
4626 + /*
4627 + * Before proceeding, make sure that the PCIe block does not have
4628 + * transactions pending.
4629 + */
4630 + poll = ixgbe_pcie_timeout_poll(hw);
4631 + for (i = 0; i < poll; i++) {
4632 + usec_delay(100);
4633 + value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4634 + if (IXGBE_REMOVED(hw->hw_addr))
4635 + goto out;
4636 + if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4637 + goto out;
4638 + }
4639 +
4640 +out:
4149 4641 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4150 4642 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4151 4643 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4152 4644 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4153 4645
4154 4646 /* Flush all writes and allow 20usec for all transactions to clear */
4155 4647 IXGBE_WRITE_FLUSH(hw);
4156 4648 usec_delay(20);
4157 4649
4158 4650 /* restore previous register values */
4159 4651 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4160 4652 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4161 4653 }
4162 4654
4655 +
4656 +/**
4657 + * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4658 + * @hw: pointer to hardware structure
4659 + * @map: pointer to u8 arr for returning map
4660 + *
4661 + * Read the rtrup2tc HW register and resolve its content into map
4662 + **/
4663 +void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4664 +{
4665 + u32 reg, i;
4666 +
4667 + reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4668 + for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4669 + map[i] = IXGBE_RTRUP2TC_UP_MASK &
4670 + (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4671 + return;
4672 +}
4673 +
4674 +void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4675 +{
4676 + u32 pfdtxgswc;
4677 + u32 rxctrl;
4678 +
4679 + rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4680 + if (rxctrl & IXGBE_RXCTRL_RXEN) {
4681 + if (hw->mac.type != ixgbe_mac_82598EB) {
4682 + pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4683 + if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4684 + pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4685 + IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4686 + hw->mac.set_lben = TRUE;
4687 + } else {
4688 + hw->mac.set_lben = FALSE;
4689 + }
4690 + }
4691 + rxctrl &= ~IXGBE_RXCTRL_RXEN;
4692 + IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4693 + }
4694 +}
4695 +
4696 +void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4697 +{
4698 + u32 pfdtxgswc;
4699 + u32 rxctrl;
4700 +
4701 + rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4702 + IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4703 +
4704 + if (hw->mac.type != ixgbe_mac_82598EB) {
4705 + if (hw->mac.set_lben) {
4706 + pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4707 + pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4708 + IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4709 + hw->mac.set_lben = FALSE;
4710 + }
4711 + }
4712 +}
4713 +
4714 +/**
4715 + * ixgbe_mng_present - returns TRUE when management capability is present
4716 + * @hw: pointer to hardware structure
4717 + */
4718 +bool ixgbe_mng_present(struct ixgbe_hw *hw)
4719 +{
4720 + u32 fwsm;
4721 +
4722 + if (hw->mac.type < ixgbe_mac_82599EB)
4723 + return FALSE;
4724 +
4725 + fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4726 + fwsm &= IXGBE_FWSM_MODE_MASK;
4727 + return fwsm == IXGBE_FWSM_FW_MODE_PT;
4728 +}
4729 +
4730 +/**
4731 + * ixgbe_mng_enabled - Is the manageability engine enabled?
4732 + * @hw: pointer to hardware structure
4733 + *
4734 + * Returns TRUE if the manageability engine is enabled.
4735 + **/
4736 +bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4737 +{
4738 + u32 fwsm, manc, factps;
4739 +
4740 + fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4741 + if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4742 + return FALSE;
4743 +
4744 + manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4745 + if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4746 + return FALSE;
4747 +
4748 + if (hw->mac.type <= ixgbe_mac_X540) {
4749 + factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4750 + if (factps & IXGBE_FACTPS_MNGCG)
4751 + return FALSE;
4752 + }
4753 +
4754 + return TRUE;
4755 +}
4756 +
4757 +/**
4758 + * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4759 + * @hw: pointer to hardware structure
4760 + * @speed: new link speed
4761 + * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
4762 + *
4763 + * Set the link speed in the MAC and/or PHY register and restarts link.
4764 + **/
4765 +s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4766 + ixgbe_link_speed speed,
4767 + bool autoneg_wait_to_complete)
4768 +{
4769 + ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4770 + ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4771 + s32 status = IXGBE_SUCCESS;
4772 + u32 speedcnt = 0;
4773 + u32 i = 0;
4774 + bool autoneg, link_up = FALSE;
4775 +
4776 + DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4777 +
4778 + /* Mask off requested but non-supported speeds */
4779 + status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4780 + if (status != IXGBE_SUCCESS)
4781 + return status;
4782 +
4783 + speed &= link_speed;
4784 +
4785 + /* Try each speed one by one, highest priority first. We do this in
4786 + * software because 10Gb fiber doesn't support speed autonegotiation.
4787 + */
4788 + if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4789 + speedcnt++;
4790 + highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4791 +
4792 + /* If we already have link at this speed, just jump out */
4793 + status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4794 + if (status != IXGBE_SUCCESS)
4795 + return status;
4796 +
4797 + if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
4798 + goto out;
4799 +
4800 + /* Set the module link speed */
4801 + switch (hw->phy.media_type) {
4802 + case ixgbe_media_type_fiber_fixed:
4803 + case ixgbe_media_type_fiber:
4804 + ixgbe_set_rate_select_speed(hw,
4805 + IXGBE_LINK_SPEED_10GB_FULL);
4806 + break;
4807 + case ixgbe_media_type_fiber_qsfp:
4808 + /* QSFP module automatically detects MAC link speed */
4809 + break;
4810 + default:
4811 + DEBUGOUT("Unexpected media type.\n");
4812 + break;
4813 + }
4814 +
4815 + /* Allow module to change analog characteristics (1G->10G) */
4816 + msec_delay(40);
4817 +
4818 + status = ixgbe_setup_mac_link(hw,
4819 + IXGBE_LINK_SPEED_10GB_FULL,
4820 + autoneg_wait_to_complete);
4821 + if (status != IXGBE_SUCCESS)
4822 + return status;
4823 +
4824 + /* Flap the Tx laser if it has not already been done */
4825 + ixgbe_flap_tx_laser(hw);
4826 +
4827 + /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4828 + * Section 73.10.2, we may have to wait up to 500ms if KR is
4829 + * attempted. 82599 uses the same timing for 10g SFI.
4830 + */
4831 + for (i = 0; i < 5; i++) {
4832 + /* Wait for the link partner to also set speed */
4833 + msec_delay(100);
4834 +
4835 + /* If we have link, just jump out */
4836 + status = ixgbe_check_link(hw, &link_speed,
4837 + &link_up, FALSE);
4838 + if (status != IXGBE_SUCCESS)
4839 + return status;
4840 +
4841 + if (link_up)
4842 + goto out;
4843 + }
4844 + }
4845 +
4846 + if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4847 + speedcnt++;
4848 + if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4849 + highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4850 +
4851 + /* If we already have link at this speed, just jump out */
4852 + status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4853 + if (status != IXGBE_SUCCESS)
4854 + return status;
4855 +
4856 + if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
4857 + goto out;
4858 +
4859 + /* Set the module link speed */
4860 + switch (hw->phy.media_type) {
4861 + case ixgbe_media_type_fiber_fixed:
4862 + case ixgbe_media_type_fiber:
4863 + ixgbe_set_rate_select_speed(hw,
4864 + IXGBE_LINK_SPEED_1GB_FULL);
4865 + break;
4866 + case ixgbe_media_type_fiber_qsfp:
4867 + /* QSFP module automatically detects link speed */
4868 + break;
4869 + default:
4870 + DEBUGOUT("Unexpected media type.\n");
4871 + break;
4872 + }
4873 +
4874 + /* Allow module to change analog characteristics (10G->1G) */
4875 + msec_delay(40);
4876 +
4877 + status = ixgbe_setup_mac_link(hw,
4878 + IXGBE_LINK_SPEED_1GB_FULL,
4879 + autoneg_wait_to_complete);
4880 + if (status != IXGBE_SUCCESS)
4881 + return status;
4882 +
4883 + /* Flap the Tx laser if it has not already been done */
4884 + ixgbe_flap_tx_laser(hw);
4885 +
4886 + /* Wait for the link partner to also set speed */
4887 + msec_delay(100);
4888 +
4889 + /* If we have link, just jump out */
4890 + status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4891 + if (status != IXGBE_SUCCESS)
4892 + return status;
4893 +
4894 + if (link_up)
4895 + goto out;
4896 + }
4897 +
4898 + /* We didn't get link. Configure back to the highest speed we tried,
4899 + * (if there was more than one). We call ourselves back with just the
4900 + * single highest speed that the user requested.
4901 + */
4902 + if (speedcnt > 1)
4903 + status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4904 + highest_link_speed,
4905 + autoneg_wait_to_complete);
4906 +
4907 +out:
4908 + /* Set autoneg_advertised value based on input link speed */
4909 + hw->phy.autoneg_advertised = 0;
4910 +
4911 + if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4912 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4913 +
4914 + if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4915 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4916 +
4917 + return status;
4918 +}
4919 +
4920 +/**
4921 + * ixgbe_set_soft_rate_select_speed - Set module link speed
4922 + * @hw: pointer to hardware structure
4923 + * @speed: link speed to set
4924 + *
4925 + * Set module link speed via the soft rate select.
4926 + */
4927 +void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4928 + ixgbe_link_speed speed)
4929 +{
4930 + s32 status;
4931 + u8 rs, eeprom_data;
4932 +
4933 + switch (speed) {
4934 + case IXGBE_LINK_SPEED_10GB_FULL:
4935 + /* one bit mask same as setting on */
4936 + rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4937 + break;
4938 + case IXGBE_LINK_SPEED_1GB_FULL:
4939 + rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4940 + break;
4941 + default:
4942 + DEBUGOUT("Invalid fixed module speed\n");
4943 + return;
4944 + }
4945 +
4946 + /* Set RS0 */
4947 + status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4948 + IXGBE_I2C_EEPROM_DEV_ADDR2,
4949 + &eeprom_data);
4950 + if (status) {
4951 + DEBUGOUT("Failed to read Rx Rate Select RS0\n");
4952 + goto out;
4953 + }
4954 +
4955 + eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4956 +
4957 + status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4958 + IXGBE_I2C_EEPROM_DEV_ADDR2,
4959 + eeprom_data);
4960 + if (status) {
4961 + DEBUGOUT("Failed to write Rx Rate Select RS0\n");
4962 + goto out;
4963 + }
4964 +
4965 + /* Set RS1 */
4966 + status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4967 + IXGBE_I2C_EEPROM_DEV_ADDR2,
4968 + &eeprom_data);
4969 + if (status) {
4970 + DEBUGOUT("Failed to read Rx Rate Select RS1\n");
4971 + goto out;
4972 + }
4973 +
4974 + eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4975 +
4976 + status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4977 + IXGBE_I2C_EEPROM_DEV_ADDR2,
4978 + eeprom_data);
4979 + if (status) {
4980 + DEBUGOUT("Failed to write Rx Rate Select RS1\n");
4981 + goto out;
4982 + }
4983 +out:
4984 + return;
4985 +}
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